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| 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor Data Sheet Advance Information Product Features s s s s s 32-Bit Parallel Architecture --Load/Store Architecture --Sixteen 32-Bit Global Registers --Sixteen 32-Bit Local Registers --1.28 Gbyte Internal Bandwidth (80 MHz) --On-Chip Register Cache Processor Core Clock --80960HA is 1x Bus Clock --80960HD is 2x Bus Clock --80960HT is 3x Bus Clock Binary Compatible with Other 80960 Processors Issue Up To 150 Million Instructions per Second High-Performance On-Chip Storage --16 Kbyte Four-Way Set-Associative Instruction Cache --8 Kbyte Four-Way Set-Associative Data Cache --2 Kbyte General Purpose RAM --Separate 128-Bit Internal Paths For Instructions/Data s s s s s 3.3 V Supply Voltage --5 V Tolerant Inputs --TTL Compatible Outputs Guarded Memory Unit --Provides Memory Protection --User/Supervisor Read/Write/Execute 32-Bit Demultiplexed Burst Bus --Per-Byte Parity Generation/Checking --Address Pipelining Option --Fully Programmable Wait State Generator --Supports 8-, 16- or 32-Bit Bus Widths --160 Mbyte/s External Bandwidth (40 MHz) High-Speed Interrupt Controller --Up to 240 External Interrupts --31 Fully Programmable Priorities --Separate, Non-maskable Interrupt Pin Dual On-Chip 32-Bit Timers --Auto Reload Capability and One-Shot --CLKIN Prescaling, /1, 2, 4 or 8 --JTAG Support - IEEE 1149.1 Compliant Notice: This document contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 272495-007 July, 1998 80960HA/HD/HT Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 80960HA/HD/HT may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 1998 *Third-party brands and names are the property of their respective owners. Advance Information Datasheet 80960HA/HD/HT Contents 1.0 2.0 About This Document .............................................................................................. 1 Intel's 80960Hx Processor......................................................................................1 2.1 2.2 The i960(R) Processor Family ................................................................................. 2 Key 80960Hx Features.......................................................................................... 2 2.2.1 Execution Architecture ............................................................................. 2 2.2.2 Pipelined, Burst Bus ................................................................................. 2 2.2.3 On-Chip Caches and Data RAM .............................................................. 3 2.2.4 Priority Interrupt Controller ....................................................................... 3 2.2.5 Guarded Memory Unit .............................................................................. 3 2.2.6 Dual Programmable Timers ..................................................................... 4 2.2.7 Processor Self Test .................................................................................. 4 Instruction Set Summary ....................................................................................... 5 Pin Descriptions .................................................................................................... 7 80960Hx Mechanical Data ..................................................................................12 3.2.1 80960Hx PGA Pinout .............................................................................12 3.2.2 80960Hx PQ4 Pinout..............................................................................18 Package Thermal Specifications .........................................................................23 Heat Sink Adhesives ...........................................................................................26 PowerQuad4 Plastic Package.............................................................................26 Stepping Register Information.............................................................................26 Sources for Accessories......................................................................................28 Absolute Maximum Ratings.................................................................................29 Operating Conditions...........................................................................................29 Recommended Connections ...............................................................................30 VCC5 Pin Requirements (VDIFF) .........................................................................30 VCCPLL Pin Requirements.................................................................................31 DC Specifications ................................................................................................32 AC Specifications ................................................................................................34 4.7.1 AC Test Conditions ................................................................................37 AC Timing Waveforms ........................................................................................38 80960Hx Boundary Scan Chain ..........................................................................76 Boundary Scan Description Language Example.................................................80 2.3 3.0 Package Information.................................................................................................6 3.1 3.2 3.3 3.4 3.5 3.6 3.7 4.0 Electrical Specifications........................................................................................29 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5.0 Bus Waveforms.........................................................................................................46 5.1 5.2 Advance Information Datasheet iii 80960HA/HD/HT Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 80960Hx Block Diagram .......................................................................................1 80960Hx 168-Pin PGA Pinout -- View from Top (Pins Facing Down) ...............12 80960Hx 168-Pin PGA Pinout -- View from Bottom (Pins Facing Up) ...............13 80960Hx 208-Pin PQ4 Pinout .............................................................................18 Measuring 80960Hx PGA Case Temperature ....................................................23 80960Hx Device Identification Register ..............................................................26 VCC5 Current-Limiting Resistor ..........................................................................30 AC Test Load ......................................................................................................37 CLKIN Waveform ................................................................................................38 Output Delay Waveform......................................................................................38 Output Delay Waveform......................................................................................38 Output Float Waveform .......................................................................................39 Input Setup and Hold Waveform .........................................................................39 NMI, XINT7:0 Input Setup and Hold Waveform ..................................................39 Hold Acknowledge Timings .................................................................................40 Bus Backoff (BOFF) Timings ..............................................................................40 TCK Waveform....................................................................................................41 Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 ....................................41 Output Delay and Output Float for TBSOV1 and TBSOF1 ......................................42 Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 ....................42 Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ......................................42 Rise and Fall Time Derating at 85C and Minimum VCC ....................................43 ICC Active (Power Supply) vs. Frequency ...........................................................43 ICC Active (Thermal) vs. Frequency ....................................................................44 Output Delay or Hold vs. Load Capacitance .......................................................44 Output Delay vs. Temperature ............................................................................45 Output Hold Times vs. Temperature ...................................................................45 Output Delay vs. VCC ..........................................................................................45 Cold Reset Waveform .........................................................................................46 Warm Reset Waveform .......................................................................................47 Entering ONCE Mode .........................................................................................48 Non-Burst, Non-Pipelined Requests without Wait States ...................................49 Non-Burst, Non-Pipelined Read Request with Wait States.................................50 Non-Burst, Non-Pipelined Write Request with Wait States .................................51 Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus .................52 Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus ......................53 Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus .................54 Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus ......................55 Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus ......................56 Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus ........................57 Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus .................58 Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ......................59 Burst, Pipelined Read Request without Wait States, 32-Bit Bus.........................60 Burst, Pipelined Read Request with Wait States, 32-Bit Bus..............................61 Burst, Pipelined Read Request with Wait States, 8-Bit Bus................................62 Burst, Pipelined Read Request with Wait States, 16-Bit Bus..............................63 Using External READY........................................................................................64 Terminating a Burst with BTERM........................................................................65 BREQ and BSTALL Operation ............................................................................66 iv Advance Information Datasheet 80960HA/HD/HT 50 51 52 53 54 56 57 58 59 BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. .......................................................................................... 67 HOLD Functional Timing .................................................................................... 68 LOCK Delays HOLDA Timing ............................................................................ 69 FAIL Functional Timing....................................................................................... 69 A Summary of Aligned and Unaligned Transfers for 32-Bit Regions ................. 70 A Summary of Aligned and Unaligned Transfers for 16-Bit Bus ........................ 72 A Summary of Aligned and Unaligned Transfers for 8-Bit Bus .......................... 73 Idle Bus Operation.............................................................................................. 74 Bus States .......................................................................................................... 75 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 80960Hx Product Description................................................................................ 1 Fail Codes For BIST (bit 7 = 1) ............................................................................. 4 Remaining Fail Codes (bit 7 = 0)........................................................................... 4 80960Hx Instruction Set ........................................................................................ 5 80960HA/HD/HT Package Types and Speeds ..................................................... 6 Pin Description Nomenclature............................................................................... 7 80960Hx Processor Family Pin Descriptions ........................................................ 8 80960Hx 168-Pin PGA Pinout -- Signal Name Order ........................................14 80960Hx 168-Pin PGA Pinout -- Pin Number Order ..........................................16 80960Hx PQ4 Pinout -- Signal Name Order ......................................................19 80960Hx PQ4 Pinout -- Pin Number Order........................................................21 Maximum TA at Various Airflows in C (PGA Package Only)..............................24 80960Hx 168-Pin PGA Package Thermal Characteristics ..................................24 Maximum TA at Various Airflows in C (PQ4 Package Only) ..............................25 80960Hx 208-Pin PQ4 Package Thermal Characteristics ..................................25 Fields of 80960Hx Device ID...............................................................................27 80960Hx Device ID Model Types........................................................................27 Device ID Version Numbers for Different Steppings ...........................................27 Operating Conditions...........................................................................................29 VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)...............30 80960Hx DC Characteristics ...............................................................................32 80960Hx AC Characteristics ...............................................................................34 AC Characteristics Notes ....................................................................................36 80960Hx Boundary Scan Test Signal Timings....................................................36 80960Hx Boundary Scan Chain ..........................................................................76 Data Sheet Version -006 to -007 Revision History..............................................96 Advance Information Datasheet v 80960HA/HD/HT 1.0 About This Document This document describes the parametric performance of Intel's 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics -- other than parametric performance -- are published in the i960(R) Hx Microprocessor User's Guide (272484). In this document, "80960Hx" and "i960 Hx processor" refer to the products described in Table 1. Throughout this document, information that is specific to each is clearly indicated. Figure 1. 80960Hx Block Diagram Instruction Prefetch Queue JTAG Port Timers Interrupt Port Programmable Interrupt Controller Multiply/Divide Unit Register-Side Execution Unit Machine Bus Memory-Side Machine Bus Instruction Cache 16 Kbyte, Four-Way Set-Associative Guarded Memory Unit Control Memory Region Configuration Address Bus Controller Bus Request Queues Data Cache 8 Kbyte, Four-Way Set-Associative 128-Bit Cache Bus Parallel Instruction Scheduler Data Data RAM - 2 Kbyte Register Cache - 5 to 15 sets Address Generation Unit Six-Port Register File 64-bit SRC1 Bus 32-bit Base Bus 64-bit SRC2 Bus 128-bit Load Bus 64-bit DST Bus 128-bit Store Bus 2.0 Intel's 80960Hx Processor Intel's 80960Hx processor provides new performance levels while maintaining backward compatibility (pin1 and software) with the i960 CA/CF processor. This newest member of the family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. This is accomplished by providing processors that can run at the bus speed or faster using Intel's clock multiplying technology (Table 1).The 80960Hx core is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler that allows the processor to sustain a throughput of two instructions every core clock, with a peak performance of three instructions per clock. The 80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external bus speed. Table 1. 80960Hx Product Description Product 80960HA 80960HD 80960HT *Processor inputs are 5 V tolerant. Core 1x 2x 3x Voltage 3.3 V 3.3 V 3.3 V * * * Operating Frequency (bus/core) 25/25, 33/33, 40/40 16/32, 25/50, 33/66, 40/80 20/60, 25/75 1. The 80960Hx is not "drop-in" compatible in an 80960Cx-based system. Customers can design systems that accept either 80960Hx or Cx processors. Advance Information Datasheet 1 80960HA/HD/HT In addition to expanded clock frequency options, the 80960Hx provides essential enhancements for an emerging class of high-performance embedded applications. Features include a larger instruction cache, data cache, and data RAM than any other 80960 processor to date. It also boasts a 32-bit demultiplexed and pipelined burst bus, fast interrupt mechanism, guarded memory unit, wait state generator, dual programmable timers, ONCE and IEEE 1149.1-compliant boundary scan test and debug support, and new instructions. 2.1 The i960(R) Processor Family The i960 processor family is a 32-bit RISC architecture created by Intel to serve the needs of embedded applications. The embedded market includes applications as diverse as industrial automation, avionics, image processing, graphics and communications. Because all members of the i960 processor family share a common core architecture, i960 applications are code-compatible. Each new processor in the family adds its own special set of functions to the core to satisfy the needs of a specific application or range of applications in the embedded market. 2.2 2.2.1 Key 80960Hx Features Execution Architecture Independent instruction paths inside the processor allow the execution of multiple, out-of-sequence instructions per clock. Register and resource scoreboarding interlocks maintain the logical integrity of sequential instructions that are being executed in parallel. To sustain execution of multiple instructions in each clock cycle, the processor decodes multiple instructions in parallel and simultaneously issues these instructions to parallel processing units. The various processing units are then able to independently access instruction operands in parallel from a common register set. Local Register Cache integrated on-chip provides automatic register management on call/return instructions. Upon a call instruction, the processor allocates a set of local registers for the called procedure, then stores the registers for the previous procedure in the on-chip register cache. As additional procedures are called, the cache stores the associated registers such that the most recently called procedure is the first available by the next return (ret) instruction. The processor can store up to fifteen register sets, after which the oldest sets are stored (spilled) into external memory. The 80960Hx supports the 80960 architecturally-defined branch prediction mechanism. This allows many branches to execute with no pipeline break. With the 80960Hx's efficient pipeline, a branch can take as few as zero clocks to execute. The maximum penalty for an incorrect prediction is two core clocks. 2.2.2 Pipelined, Burst Bus A 32-bit high performance bus controller interfaces the 80960Hx core to the external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 160 Mbytes per second (at a 40 MHz external bus clock frequency). A key advantage of this design is its versatility. The user can independently program the physical and logical attributes of system memory. Physical attributes include wait state profile, bus width, and parity. Logical attributes include cacheability and Big or Little Endian byte order. Internally programmable wait states and 16 separately configurable physical memory regions allow the processor to interface with a variety of memory 2 Advance Information Datasheet 80960HA/HD/HT subsystems with minimum system complexity. To reduce the effect of wait states, the bus design is decoupled from the core. This lets the processor execute instructions while the bus performs memory accesses independently. The Bus Controller's key features include: * * * * * * * * 2.2.3 Demultiplexed, Burst Bus to support most efficient DRAM access modes Address Pipelining to reduce memory cost while maintaining performance 32-, 16- and 8-bit modes to facilitate I/O interfacing Full internal wait state generation to reduce system cost Little and Big Endian support Unaligned Access support implemented in hardware Three-deep request queue to decouple the bus from the core Independent physical and logical address space characteristics On-Chip Caches and Data RAM As shown in Figure 1, the 80960Hx provides generous on-chip cache and storage features to decouple CPU execution from the external bus. The processor includes a 16 Kbyte instruction cache, an 8 Kbyte data cache and 2 Kbytes of Data RAM. The caches are organized as 4-way set associative. Stores that hit the data cache are written through to memory. The data cache performs write allocation on cache misses. A fifteen-set stack frame cache allows the processor to rapidly allocate and deallocate local registers. All of the on-chip RAM sustains a 4-word (128-bit) access every clock cycle. 2.2.4 Priority Interrupt Controller The interrupt unit provides the mechanism for the low latency and high throughput interrupt service essential for embedded applications. A priority interrupt controller provides full programmability of 240 interrupt sources with a typical interrupt task switch (latency) time of 17 core clocks. The controller supports 31 priority levels. Interrupts are prioritized and signaled within 10 core clocks of the request. If the interrupt has a higher priority than the processor priority, the context switch to the interrupt routine would typically complete in another 7 bus clocks. External agents post interrupts via the 8-bit external interrupt port. The Interrupt unit also handles the two internal sources from the Timers. Interrupts can be level- or edge-triggered. 2.2.5 Guarded Memory Unit The Guarded Memory Unit (GMU) provides memory protection without the address translation found in Memory Management Units. The GMU contains two memory protection schemes: one prevents illegal memory accesses, the other detects memory access violations. Both signal a fault to the processor. The programmable protection modes are: user read, write or execute; and supervisor read, write or execute. Advance Information Datasheet 3 80960HA/HD/HT 2.2.6 Dual Programmable Timers The processor provides two independent 32-bit timers, with four programmable clock rates. The user configures the timers via the Timer Unit registers. These registers are memory-mapped within the 80960Hx, addressable on 32-bit boundaries. The timers have a single-shot mode and auto-reload capabilities for continuous operation. Each timer has an independent interrupt request to the processor's interrupt controller. 2.2.7 Processor Self Test When a system error is detected, the FAIL pin is asserted, a fail code message is driven onto the address bus, and the processor stops execution at the point of failure. The only way to resume normal operation is to perform a RESET operation. Because System Error generation can occur sometime after the bus confidence test and even after initialization during normal processor operation, the FAIL pin is HIGH (logic "1") before the detection of a System Error. The processor uses only one read bus-transaction to signal the fail code message; the address of the bus transaction is the fail code itself. The fail code is of the form: 0xfeffffnn; bits 6 to 0 contain a mask recording the possible failures. Bit 7, when set to 1, indicates that the mask contains failures from the internal Built-In Self-Test (BIST); when 0, the mask indicates other failures. Ignore reserved bits 0 and 1. Also ignore bits 5 and 6 when bit 7 is clear (=0). The mask is shown in Table 2 and Table 3. Table 2. Fail Codes For BIST (bit 7 = 1) Bit 6 5 4 3 2 1 0 When Set: On-chip Data-RAM failure detected by BIST. Internal Microcode ROM failure detected by BIST. Instruction cache failure detected by BIST. Data cache failure detected by BIST. Local-register cache or processor core failure detected by BIST. Reserved. Always zero. Reserved. Always zero. Table 3. Remaining Fail Codes (bit 7 = 0) Bit 6 5 4 3 2 1 0 Reserved. Always one. Reserved. Always one. A data structure within the IMI is not aligned to a word boundary. A System Error during normal operation has occurred. The Bus Confidence test has failed. Reserved. Always zero. Reserved. Always zero. When Set: 4 Advance Information Datasheet 80960HA/HD/HT 2.3 Instruction Set Summary Table 4 summarizes the 80960Hx instruction set by logical groupings. Table 4. 80960Hx Instruction Set Data Movement Add Subtract Multiply Divide Remainder Load Store Move Load Address Conditional Select(2) Modulo Shift Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Rotate Conditional Add(2) Conditional Subtract(2) Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Compare Byte (2) Arithmetic Logical Bit / Bit Field / Byte And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal Byte Swap(2) Branch Call/Return Fault Call Unconditional Branch Conditional Branch Compare and Branch Call Extended Call System Return Branch and Link Conditional Fault Synchronize Faults Compare Short(2) Test Condition Code Check Bit Debug Processor Mgmt Flush Local Registers Atomic Cache Control Modify Trace Controls Mark Force Mark Modify Arithmetic Controls Modify Process Controls Interrupt Enable/ Disable(1,2) System Control(1) Atomic Add Atomic Modify Instruction Cache Control(1,2) Data Cache Control(1,2) NOTES: 1. 80960Hx extensions to the 80960 core instruction set. 2. 80960Hx extensions to the 80960Cx instruction set. Advance Information Datasheet 5 80960HA/HD/HT 3.0 Package Information This section describes the pins, pinouts and thermal characteristics for the 80960Hx in the 168-pin ceramic Pin Grid Array (PGA) package, 208-pin PowerQuad2* (PQ4). For complete package specifications and information, see the Intel Packaging Handbook (Order# 240800). The 80960HA/HD/HT is offered with eigth speeds and two package types (Table 5). Both the 168-pin ceramic Pin Grid Array (PGA) and the 208-pin PowerQuad2* (PQ4) devices are specified for operation at VCC = 3.3 V 0.15 V over a case temperature range of 0 to 85C. Table 5. 80960HA/HD/HT Package Types and Speeds Package/Name Device Core Speed (MHz) 25 80960HA 33 40 32 168L PGA 80960HD 66 80 60 80960HT 75 25 80960HA 33 40 32 208L PQFP (also known as PQ4) 50 80960HD 66 80 60 80960HT 75 25 FC80960HT75 S L2GT 33 40 20 FC80960HD66 S L2GN FC80960HD80 S L2LZ FC80960HT60 S L2G2 16 25 25 A80960HT75 S L2GP FC80960HA25 S L2GU FC80960HA33 S L2GV FC80960HA40 S L2GW FC80960HD32 S L2GL FC80960HD50 S L2GM 33 40 20 A80960HD66 S L2GJ A80960HD80 S L2GK A80960HT60 50 16 25 Bus Speed (MHz) Order # A80960HA25 S L2GX A80960HA33 S L2GY A80960HA40 S L2GZ A80960HD32 S L2GG A80960HD50 S L2GH 6 Advance Information Datasheet 80960HA/HD/HT 3.1 Pin Descriptions This section defines the 80960Hx pins. Table 6 presents the legend for interpreting the pin descriptions in Table 7. All pins float while the processor is in the ONCE mode, except TDO, which can be driven active according to normal JTAG specifications. Table 6. Pin Description Nomenclature Symbol I O I/O S(E) S(L) A(E) A(L) Input only pin. Output only pin. Pin can be input or output. Pin must be connected as indicated for proper device functionality. Synchronous edge sensitive input. This input must meet the setup and hold times relative to CLKIN to ensure proper operation of the processor. Synchronous level sensitive input. This input must meet the setup and hold times relative to CLKIN to ensure proper operation of the processor. Asynchronous edge-sensitive input. Asynchronous level-sensitive input. While the processor bus is in the HOLD state (HOLDA asserted), the pin: H(1) is driven to VCC H(0) is driven to VSS H(Z) floats H(Q) continues to be a valid output While the processor is in the bus backoff state (BOFF asserted), the pin: B(1) is driven to VCC B(0) is driven to VSS B(Z) floats B(Q) continues to be a valid output While the processor's RESET pin is asserted, the pin: R(1) is driven to VCC R(0) is driven to VSS R(Z) floats R(Q) continues to be a valid output Description H(...) B(...) R(...) Advance Information Datasheet 7 80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 1 of 4) Name Type O A31:2 H(Z) B(Z) R(Z) I/O D31:0 S(L) H(Z) B(Z) R(Z) Description ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most significant address bit and A2 is the least significant. During a bus access, A31:2 identify all external addresses to word (4-byte) boundaries. The byte enable signals indicate the selected byte in each word. During burst accesses, A3 and A2 increment to indicate successive addresses. DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width configuration. The least significant bit of the data is carried on D0 and the most significant on D31. The lower 8 data lines (D7:0) are used when the bus is configured for 8-bit data. When configured for 16-bit data, D15:0 are used. DATA PARITY carries parity information for the data bus. Each parity bit is assigned a group of 8 data bus pins as follows: I/O DP3:0 S(L) H(Z) B(Z) R(Z) DP3 generates/checks parity for D31:24 DP2 generates/checks parity for D23:16 DP1 generates/checks parity for D15:8 DP0 generates/checks parity for D7:0 Parity information is generated for a processor write cycle and is checked for a processor read cycle. Parity checking and polarity are programmable. Parity generation/checking is only performed for the size of the data accessed. PARITY CHECK indicates the result of a parity check operation. An asserted PCHK indicates that the previous bus read access resulted in a parity check error. BYTE ENABLES select which of the four bytes addressed by A31:2 are active during a bus access. Byte enable encoding is dependent on the bus width of the memory region accessed: O PCHK H(Q) B(Q) R(1) O BE3:0 H(Z) B(Z) R(1) 32-bit bus: BE3 enables D31:24 BE2 enables D23:16 BE1 enables D15:8 BE0 enables D7:0 16-bit bus: BE3 becomes Byte High Enable (enables D15:8) BE2 is not used (state is undefined) BE1 becomes Address Bit 1 (A1) BE0 becomes Byte Low Enable (enables D7:0) 8-bit bus: BE3 is not used (state is undefined) BE2 is not used (state is undefined) BE1 Address Bit 1 (A1) BE0 Address Bit 0 (A0) WRITE/READ is low for read accesses and high for write accesses. W/R becomes valid during the address phase of a bus cycle and remains valid until the end of the cycle for non-pipelined accesses. For pipelined accesses, W/R changes state when the next address is presented. 0= Read 1= Write DATA/CODE indicates that a bus access is a data access or an instruction access. D/C has the same timing as W/R. 0 = Code 1 = Data O W/R H(Z) B(Z) R(0) O D/C H(Z) B(Z) R(0) 8 Advance Information Datasheet 80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 2 of 4) Name Type O SUP H(Z) B(Z) R(1) O ADS H(Z) B(Z) R(1) ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS is asserted for the first clock of a bus access. READY, when enabled for a memory region, is asserted by the memory subsystem to indicate the completion of a data transfer. READY is used to indicate that read data on the bus is valid, or that a write transfer has completed. READY works in conjunction with the internal wait state generator to accommodate various memory speeds. READY is sampled after any programmed wait states: During each data cycle of a burst access During the data cycle of a non-burst access I S(L) O WAIT H(Z) B(Z) R(1) O BLAST H(Z) B(Z) R(1) BURST TERMINATE, when enabled for a memory region, is asserted by the memory subsystem to terminate a burst access in progress. When BTERM is asserted, the current burst access is terminated and another address cycle occurs. WAIT indicates the status of the internal wait-state generator. WAIT is asserted when the internal wait state generator generates NWAD, NRAD, NWDD and NRDD wait states. WAIT can be used to derive a write data strobe. BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last data transfer of burst and non-burst accesses after the internal wait-state generator reaches zero. BLAST remains active as long as wait states are inserted via the READY pin. BLAST becomes inactive after the final data transfer in a bus cycle. DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used with DEN to provide control for data transceivers connected to the data bus. DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is driven high when the processor is "transmitting" data (a store cycle). DT/R only changes state when DEN is high. 0 = Data Receive 1 = Data Transmit DATA ENABLE indicates data transfer cycles during a bus access. DEN is asserted at the start of the first data cycle in a bus access and de-asserted at the end of the last data cycle. DEN remains asserted for an entire bus request, even when that request spans several bus accesses. For example, a ldq instruction starting at an unaligned quad word boundary is one bus request spanning at least two bus accesses. DEN remains asserted throughout all the accesses (including ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is used with DT/R to provide control for data transceivers connected to the data bus. DEN remains asserted for sequential reads from pipelined memory regions. BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK may be used by the memory subsystem to prevent external agents from accessing memory that is currently involved in an atomic operation (e.g., a semaphore). LOCK is asserted in the first clock of an atomic operation and de-asserted when BLAST is deasserted in the last bus cycle. Description SUPERVISOR ACCESS indicates whether the current bus access originates from a request issued while in supervisor mode or user mode. SUP can be used by the memory subsystem to isolate supervisor code and data structures from non-supervisor access. 0 = Supervisor Mode 1 = User Mode READY I S(L) BTERM O DT/R H(Z) B(Z) R(0) O DEN H(Z) B(Z) R(1) O LOCK H(Z) B(Z) R(1) Advance Information Datasheet 9 80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 3 of 4) Name Type Description HOLD REQUEST signals that an external agent requests access to the processor's address, data, and control buses. When HOLD is asserted, the processor: HOLD I S(L) Completes the current bus request. Asserts HOLDA and floats the address, data, and control buses. When HOLD is deasserted, the HOLDA pin is deasserted and the processor reassumes control of the address, data, and control pins. O HOLDA H(1) B(0) R(Q) HOLD ACKNOWLEDGE indicates to an external master that the processor has relinquished control of the bus. The processor grants HOLD requests and enters the HOLDA state while the RESET pin is asserted. HOLDA is never granted while LOCK is asserted. BUS BACKOFF forces the processor to immediately relinquish control of the bus on the next clock cycle. When READY/BTERM is enabled and: BOFF I S(L) When BOFF is asserted, the address, data, and control buses are floated on the next clock cycle and the current access is aborted. When BOFF is deasserted, the processor resumes by regenerating the aborted bus access. See Figure 16 on page 40 for BOFF timing requirements. O BREQ H(Q) B(Q) R(0) O BSTALL H(Q) B(Q) R(0) BUS REQUEST indicates that a bus request is pending in the bus controller. BREQ does not indicate whether or not the processor is stalled. See BSTALL for processor stall status. BREQ can be used with BSTALL to indicate to an external bus arbiter the processor's bus ownership requirements. BUS STALL indicates that the processor has stalled pending the result of a request in the bus controller. When BSTALL is asserted, the processor must regain bus ownership to continue processing (i.e., it can no longer execute strictly out of on-chip cache memory). CYCLE TYPE indicates the type of bus cycle currently being started or processor state. CT3:0 encoding follows: Cycle Type O CT3:0 H(Z) B(Z) R(Z) Program-initiated access using 8-bit bus Program-initiated access using 16-bit bus Program-initiated access using 32-bit bus Event-initiated access using 8-bit bus Event-initiated access using 16-bit bus Event-initiated access using 32-bit bus Reserved Reserved for future products Reserved ADSCT3:0 00000 00001 00010 00100 00101 00110 00X11 01XXX 1XXXX EXTERNAL INTERRUPT pins are used to request interrupt service. These pins can be configured in three modes: I XINT7:0 A(E) A(L) Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs can be programmed to be level (low or high) or edge (rising or falling) sensitive. Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins are level sensitive in this mode. Mixed Mode: The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act as the five most significant bits of a vectored source. The least significant bits of the vectored source are set to "010" internally. NMI I A(E) NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI is the highest priority interrupt source. NMI is falling edge triggered. 10 Advance Information Datasheet 80960HA/HD/HT Table 7. 80960Hx Processor Family Pin Descriptions (Sheet 4 of 4) Name Type Description CLOCK INPUT provides the time base for the 80960Hx. All internal circuitry is synchronized to CLKIN. All input and output timings are specified relative to CLKIN. For the 80960HD, the 2x internal clock is derived by multiplying the CLKIN frequency by 2. For the 80960HT, the 3x internal clock is derived by multiplying the CLKIN frequency by 3. RESET forces the device into reset. RESET causes all external and internal signals to return to their reset state (if defined). The rising edge of RESET starts the processor boot sequence. SELF TEST, when asserted during the rising edge of RESET, causes the processor to execute its built in self-test. FAIL indicates a failure of the processor's built-in self-test performed during initialization. FAIL is asserted immediately out of reset and toggles during self-test to indicate the status of individual tests. If self-test passes, FAIL is de-asserted and the processor branches to the user's initialization code. When self-test fails, the FAIL pin asserts and the processor ceases execution. ON-CIRCUIT EMULATION control: the processor samples this pin during reset. If it is asserted low at the end of reset, the processor enters ONCE mode. In ONCE mode, the processor stops all clocks and floats all output pins except the TDO pin. ONCE uses an internal pull-up resistor; see RPU definition in Table 21 "80960Hx DC Characteristics" on page 32. Pull this pin high when not in use. TEST CLOCK provides the clocking function for IEEE 1149.1 Boundary Scan testing. TEST DATA INPUT is the serial input pin for IEEE 1149.1 Boundary Scan testing. TDI uses an internal pull-up resistor; see RPU definition in Table 21 "80960Hx DC Characteristics" on page 32. TEST DATA OUTPUT is the serial output pin for IEEE 1149.1 Boundary Scan testing. ONCE does not disable this pin. TEST RESET asynchronously resets the Test Access Port (TAP) controller. TRST must be held low at least 10,000 clock cycles after power-up. One method is to provide TRST with a separate power-on-reset circuit. TRST includes an internal pull-up resistor; see RPU definition in Table 21 "80960Hx DC Characteristics" on page 32. Pull this pin low when not in use. TEST MODE SELECT is sampled at the rising edge of TCK. TCK controls the sequence of TAP controller state changes for IEEE 1149.1 Boundary Scan testing. TMS uses an internal pull-up resistor; see RPU definition in Table 21 "80960Hx DC Characteristics" on page 32. 5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O buffers. Connect this signal to +5 V for use with inputs which exceed 3.3 V. When all inputs are from 3.3 V components, connect this signal to 3.3 V. PLL VOLTAGE is the +3.3 VDC analog input for the PLL. VOLTAGE DETECT signal allows external system logic to distinguish between a 5 V 80960Cx processor and the 3.3 V 80960Hx processor. This signal is active low for a 3.3 V 80960Hx (it is high impedance for 5 V 80960Cx). This pin is available only on the PGA version. 0 = 80960Hx 1 = 80960Cx CLKIN I RESET I A(L) I S(L) O STEST FAIL H(Q) B(Q) R(0) ONCE I TCK I TDI I TDO O TRST I TMS I VCC5 VCCPLL I I VOLDET O Advance Information Datasheet 11 80960HA/HD/HT 3.2 3.2.1 80960Hx Mechanical Data 80960Hx PGA Pinout Figure 2 depicts the complete 80960Hx PGA pinout as viewed from the top side of the component (i.e., pins facing down). Figure 3 shows the complete 80960Hx PGA pinout as viewed from the pin-side of the package (i.e., pins facing up). Table 9 lists the 80960Hx pin names with package location. See Section 4.3, "Recommended Connections" on page 30 for specifications and recommended connections. Figure 2. 80960Hx 168-Pin PGA Pinout -- View from Top (Pins Facing Down) S 1 2 3 4 R Q P N M L K J H G F E D C B A 1 2 3 4 5 6 TRST TDI D25 D24 D21 D19 D17 D16 D15 D13 D12 D11 D9 D8 D7 D5 D3 BOFF VSS FAIL D29 D27 D23 D20 D18 VCC VSS D14 VCC VSS VCC VSS D10 VCC VSS D6 D4 D2 D1 STEST READY D31 D26 D22 VCC VSS VSS VCC D0 NC ONCE VSS VCC5 VCC VSS VSS VSS DP1 DP3 DP0 DP2 HOLDA BTERM D28 5 BE3 HOLD D30 VCC VSS VSS VSS VSS VSS SUP TCK TMS VOLDET 6 BE2 ADS VCC VCC 7 BE1 8 BLAST 9 DEN BE0 VCC VCC 10 W/R 11 DT/R i A20 A19 VCC A16 VSS VCC A17 A15 A14 A80960Hx M VCC PCHK VCC 7 8 TDO 9 (c) 19xx NC VSS VCCPLL VSS VSS CLKIN VCC VCC NC 10 NC XXXXXXXX SS 11 CTO CT1 12 13 14 15 16 17 WAIT BSTALL 12 13 14 15 16 D/C BREQ A30 CT2 LOCK A29 A28 VCC VSS A13 VSS VCC VSS VCC VSS VCC VSS A7 VSS VCC VCC A4 NMI A2 NC CT3 XINT1 A31 A27 A26 A23 A24 A21 XINT4 XINT0 XINT6 XINT3 RESET 17 A25 A22 A18 A12 A11 A10 A9 A8 A6 A5 A3 XINT7 XINT5 XINT2 S R Q P N M L K J H G F E D C B A 12 Advance Information Datasheet 80960HA/HD/HT Figure 3. 80960Hx 168-Pin PGA Pinout -- View from Bottom (Pins Facing Up) A 1 VSS B C D E F G H J K L M N P Q R S 1 BOFF D3 D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25 2 FAIL STEST D1 D2 D4 D6 VCC VSS D10 VCC VSS VCC VSS D14 VCC VSS D18 D20 D23 D27 D29 2 3 DP0 DP1 DP3 ONCE VSS VCC5 NC D0 VCC VSS VSS VCC D22 D26 D31 READY DP2 3 4 5 6 7 TDI VCC VSS VSS VSS VSS VCC VCC BE0 BE1 4 D28 BTERM HOLDA VOLDET TCK 5 D30 HOLD BE3 TRST TMS VCC 6 VCC ADS BE2 7 8 TDO PCHK VCC VSS VSS 8 9 NC Package Lid BLAST 9 DEN 10 NC VCCPLL VSS 10 VSS VSS VCC VCC W/R 11 CT0 VCC VCC NC VSS VSS CLKIN DT/R 11 12 CT1 SUP BSTALL WAIT 12 13 CT2 A30 BREQ D/C 13 14 CT3 NC VCC NMI VCC A4 VSS VCC A6 VSS A7 VSS VCC A9 VSS VCC A10 VSS VCC A11 VSS A13 VSS VCC A14 VCC A16 A20 A28 A29 LOCK 14 15 XINT1 XINT0 XINT4 A24 A26 A23 A31 15 16 RESET XINT3 XINT6 A2 A19 A21 A27 16 17 XINT2 XINT5 XINT7 A3 A5 A8 A12 A15 A17 A18 A22 A25 17 A B C D E F G H J K L M N P Q R S Advance Information Datasheet 13 80960HA/HD/HT Table 8. 80960Hx 168-Pin PGA Pinout -- Signal Name Order (Sheet 1 of 2) Signal Name A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 PGA Pin D16 D17 E16 E17 F17 G16 G17 H17 J17 K17 L17 L16 M17 N17 N16 P17 Q17 P16 P15 Q16 R17 R16 Q15 S17 R15 S16 Q14 R14 Q13 S15 Signal Name ADS BE0 BE1 BE2 BE3 BLAST BOFF BREQ BSTALL BTERM CLKIN CT0 CT1 CT2 CT3 D/C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 PGA Pin R6 R9 S7 S6 S5 S8 B1 R13 R12 R4 C13 A11 A12 A13 A14 S13 E3 C2 D2 C1 E2 D1 F2 E1 F1 G1 H2 H1 J1 K1 Signal Name D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DEN DP0 DP1 DP2 DP3 DT/R FAIL -- -- -- HOLD HOLDA PGA Pin L2 L1 M1 N1 N2 P1 P2 Q1 P3 Q2 R1 S1 Q3 R2 Q4 S2 Q5 R3 S9 A3 B3 A4 B4 S11 A2 -- -- -- R5 S4 Signal Name LOCK NC NC NC NC NC NMI ONCE PCHK READY RESET STEST SUP TCK TDI TDO TMS TRST VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PGA Pin S14 A9 A10 B13 B14 D3 D15 C3 B8 S3 A16 B2 Q12 B5 A7 A8 B6 A6 B7 B9 B11 B12 C6 C14 E15 F3 F16 G2 H16 J2 14 Advance Information Datasheet 80960HA/HD/HT Table 8. 80960Hx 168-Pin PGA Pinout -- Signal Name Order (Sheet 2 of 2) Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC5 PGA Pin J16 K2 K16 M2 M16 N3 N15 Q6 R7 R8 R10 R11 C5 Signal Name VCCPLL VOLDET VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PGA Pin B10 A5 A1 C4 C7 C8 C9 C10 C11 C12 F15 G3 G15 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PGA Pin H3 H15 J3 J15 K3 K15 L3 L15 M3 M15 Q7 Q8 Q9 Signal Name VSS VSS W/R WAIT XINT0 XINT1 XINT2 XINT3 XINT4 XINT5 XINT6 XINT7 -- PGA Pin Q10 Q11 S10 S12 B15 A15 A17 B16 C15 B17 C16 C17 -- Advance Information Datasheet 15 80960HA/HD/HT Table 9. 80960Hx 168-Pin PGA Pinout -- Pin Number Order (Sheet 1 of 2) PGA Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 Signal Name VSS FAIL DP0 DP2 VOLDET TRST TDI TDO NC NC CT0 CT1 CT2 CT3 XINT1 RESET XINT2 BOFF STEST DP1 DP3 TCK TMS VCC PCHK VCC VCCPLL VCC VCC NC PGA Pin B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 D17 E1 E2 E3 Signal Name NC XINT0 XINT3 XINT5 D3 D1 ONCE VSS VCC5 VCC VSS VSS VSS VSS VSS VSS CLKIN VCC XINT4 XINT6 XINT7 D5 D2 NC NMI A2 A3 D7 D4 D0 PGA Pin E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 G15 G16 G17 H1 H2 H3 H15 H16 H17 J1 J2 J3 J15 J16 J17 K1 K2 K3 Signal Name VCC A4 A5 D8 D6 VCC VSS VCC A6 D9 VCC VSS VSS A7 A8 D11 D10 VSS VSS VCC A9 D12 VCC VSS VSS VCC A10 D13 VCC VSS PGA Pin K15 K16 K17 L1 L2 L3 L15 L16 L17 M1 M2 M3 M15 M16 M17 N1 N2 N3 N15 N16 N17 P1 P2 P3 P15 P16 P17 Q1 Q2 Q3 Signal Name VSS VCC A11 D15 D14 VSS VSS A13 A12 D16 VCC VSS VSS VCC A14 D17 D18 VCC VCC A16 A15 D19 D20 D22 A20 A19 A17 D21 D23 D26 16 Advance Information Datasheet 80960HA/HD/HT Table 9. 80960Hx 168-Pin PGA Pinout -- Pin Number Order (Sheet 2 of 2) PGA Pin Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Signal Name D28 D30 VCC VSS VSS VSS VSS VSS SUP A30 A28 A24 PGA Pin Q16 Q17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 Signal Name A21 A18 D24 D27 D31 BTERM HOLD ADS VCC VCC BE0 VCC PGA Pin R11 R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 Signal Name VCC BSTALL BREQ A29 A26 A23 A22 D25 D29 READY HOLDA BE3 PGA Pin S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Signal Name BE2 BE1 BLAST DEN W/R DT/R WAIT D/C LOCK A31 A27 A25 Advance Information Datasheet 17 80960HA/HD/HT 3.2.2 80960Hx PQ4 Pinout Figure 4. 80960Hx 208-Pin PQ4 Pinout PIN 156 VSS VSS VCC VCC VSS A2 A3 VCC VSS A4 A5 A6 A7 VCC VSS A8 A9 A10 A11 VCC VSS A12 A13 A14 A15 VCC VSS VSS VCC A16 A17 A18 A19 VCC VSS A20 A21 A22 A23 VCC VSS VCC VSS A24 A25 A26 A27 VCC VSS A28 A29 A30 PIN 105 PIN 104 PIN 157 VSS VCC NMI XINT7 XINT6 XINT5 XINT4 VSS VCC XINT3 XINT2 XINT1 XINT0 VSS VCC VSS VCC RESET CLKIN VCC VCCPLL VSS VCC CT3 CT2 CT1 CT0 VSS VCC VSS VCC TDO PCHK VSS TDI TMS TRST TCK VSS VCC VCC5 VSS VCC VSS VCC DP3 DP2 VCC VSS DP0 DP1 STEST A31 VSS VCC VCC BREQ LOCK VSS SUP D/C VCC VSS VSS VCC BSTALL WAIT DT/R W/R VCC VSS i960 (R) DEN BLAST BE0 BE1 VCC VSS BE2 BE3 ADS VCC VSS VCC VSS HOLDA VCC VSS HOLD READY BTERM VCC VSS D31 D30 D29 D28 VCC VCC VSS D27 D26 D25 D24 VSS i FAIL ONCE VSS VSS VCC BOFF VCC D0 VCC VSS VSS VCC D2 D3 VSS VCC VSS VCC D1 FC80960Hx XXXXXXXX SS M (c) 19xx D8 D9 D10 D11 VSS VCC VSS VCC D12 D13 D14 D15 VCC D16 D17 D18 D19 VSS VCC D20 VCC VSS VSS VCC D7 VSS VCC PIN 208 PIN 1 D21 D22 D23 D4 D5 D6 PIN 53 PIN 52 18 Advance Information Datasheet 80960HA/HD/HT Table 10. 80960Hx PQ4 Pinout -- Signal Name Order (Sheet 1 of 2) Signal Name A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 ADS PQ4 Pin 151 150 147 146 145 144 141 140 139 138 135 134 133 132 127 126 125 124 121 120 119 118 113 112 111 110 107 106 105 104 77 Signal Name BE0 BE1 BE2 BE3 BLAST BOFF BREQ BSTALL BTERM CLKIN CT0 CT1 CT2 CT3 D/C D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PQ4 Pin 83 82 79 78 84 10 100 91 67 175 183 182 181 180 96 12 13 14 15 20 21 22 23 26 27 28 29 34 35 36 37 Signal Name D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 DEN DP0 DP1 DP2 DP3 DT/R FAIL -- -- -- HOLD HOLDA LOCK NMI ONCE PQ4 Pin 39 40 41 42 45 50 51 52 54 55 56 57 61 62 63 64 85 206 207 203 202 89 5 -- -- -- 69 72 99 159 6 Signal Name PCHK READY RESET STEST SUP TCK TDI TDO TMS TRST VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PQ4 Pin 189 68 174 208 97 194 191 188 192 193 1 4 9 11 17 19 25 31 33 38 44 46 49 59 60 66 71 74 76 81 87 Advance Information Datasheet 19 80960HA/HD/HT Table 10. 80960Hx PQ4 Pinout -- Signal Name Order (Sheet 2 of 2) Signal Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC PQ4 Pin 92 95 101 102 109 115 117 123 128 131 137 143 149 153 154 158 165 171 173 176 179 185 Signal Name VCC VCC VCC VCC VCC VCC5 VCCPLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PQ4 Pin 187 196 199 201 204 197 177 2 3 7 8 16 18 24 30 32 43 47 48 53 58 65 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PQ4 Pin 70 73 75 80 86 93 94 98 103 108 114 116 122 129 130 136 142 148 152 155 156 157 Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS W/R WAIT XINT0 XINT1 XINT2 XINT3 XINT4 XINT5 XINT6 XINT7 -- PQ4 Pin 164 170 172 178 184 186 190 195 198 200 205 88 90 169 168 167 166 163 162 161 160 -- 20 Advance Information Datasheet 80960HA/HD/HT Table 11. 80960Hx PQ4 Pinout -- Pin Number Order (Sheet 1 of 2) PQ4 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Signal Name VCC VSS VSS VCC FAIL ONCE VSS VSS VCC BOFF VCC D0 D1 D2 D3 VSS VCC VSS VCC D4 D5 D6 D7 VSS VCC D8 D9 D10 D11 VSS PQ4 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Signal Name VCC VSS VCC D12 D13 D14 D15 VCC D16 D17 D18 D19 VSS VCC D20 VCC VSS VSS VCC D21 D22 D23 VSS D24 D25 D26 D27 VSS VCC VCC PQ4 Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 Signal Name D28 D29 D30 D31 VSS VCC BTERM READY HOLD VSS VCC HOLDA VSS VCC VSS VCC ADS BE3 BE2 VSS VCC BE1 BE0 BLAST DEN VSS VCC W/R DT/R WAIT PQ4 Pin 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Signal Name BSTALL VCC VSS VSS VCC D/C SUP VSS LOCK BREQ VCC VCC VSS A31 A30 A29 A28 VSS VCC A27 A26 A25 A24 VSS VCC VSS VCC A23 A22 A21 Advance Information Datasheet 21 80960HA/HD/HT Table 11. 80960Hx PQ4 Pinout -- Pin Number Order (Sheet 2 of 2) PQ4 Pin 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 Signal Name A20 VSS VCC A19 A18 A17 A16 VCC VSS VSS VCC A15 A14 A13 A12 VSS VCC A11 A10 A9 A8 VSS PQ4 Pin 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 Signal Name VCC A7 A6 A5 A4 VSS VCC A3 A2 VSS VCC VCC VSS VSS VSS VCC NMI XINT7 XINT6 XINT5 XINT4 VSS PQ4 Pin 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 Signal Name VCC XINT3 XINT2 XINT1 XINT0 VSS VCC VSS VCC RESET CLKIN VCC VCCPLL VSS VCC CT3 CT2 CT1 CT0 VSS VCC VSS PQ4 Pin 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Name VCC TDO PCHK VSS TDI TMS TRST TCK VSS VCC VCC5 VSS VCC VSS VCC DP3 DP2 VCC VSS DP0 DP1 STEST 22 Advance Information Datasheet 80960HA/HD/HT 3.3 Package Thermal Specifications The 80960Hx is specified for operation when TC (case temperature) is within the range of 0C-85C. TC may be measured in any environment to determine whether the 80960Hx is within the specified operating range. Measure the case temperature at the center of the top surface, opposite the pins. Refer to Figure 5. TA (ambient temperature) is calculated from CA (thermal resistance from case to ambient) using the equation: TA = TC - P*CA Table 12 shows the maximum TA allowable (without exceeding TC) at various airflows and operating frequencies (fCLKIN). Note that TA is greatly improved by attaching fins or a heatsink to the package. P (maximum power consumption) is calculated by using the typical ICC as tabulated in Section 4.6, "DC Specifications" on page 32 and VCC of 3.3 V. Figure 5. Measuring 80960Hx PGA Case Temperature Measure PGA/PQ4 temperature at center of top surface Advance Information Datasheet 23 80960HA/HD/HT Table 12. Maximum TA at Various Airflows in C (PGA Package Only) Airflow-ft/min (m/sec) fCLKIN (MHz) TA with Heatsink* TA without Heatsink TA with Heatsink* Core 2X Bus Clock 25 33 40 25 33 40 16 25 33 40 16 25 33 40 20 25 20 25 0 (0) 69 63 59 64 56 50 68 58 49 41 62 49 38 27 53 45 43 33 200 (1.01) 74 70 67 67 62 56 73 66 60 55 66 56 46 38 63 58 51 42 400 (2.03) 78 75 73 71 67 63 77 73 69 65 71 62 55 48 71 67 58 51 600 (3.04) 79 77 75 74 70 67 79 75 71 68 73 66 60 55 73 70 63 58 800 (4.06) 80 79 77 75 72 69 80 77 74 72 75 68 63 58 76 73 66 61 1000 (5.07) 80 79 77 76 74 71 80 77 74 72 76 71 66 62 76 73 68 64 Core 1X Bus Clock TA without Heatsink TA with Heatsink* TA without Heatsink Core 3X Bus Clock *0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Table 13. 80960Hx 168-Pin PGA Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter 0 (0) 1.5 200 (1.01) 1.5 400 (2.03) 1.5 600 (3.07) 1.5 800 (4.06) 1.5 1000 (5.07) 1.5 JA JC Junction-to-Case (Case measured as shown in Figure 5) Case-to-Ambient (No Heatsink) Case-to-Ambient (With Heatsink)* 17 13 14 9 11 6 9 5 8 4 7 4 NOTES: 1. This table applies to 80960Hx PGA plugged into socket or soldered directly to board. 2. JA = JC + CA *0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). 24 Advance Information Datasheet 80960HA/HD/HT Table 14. Maximum TA at Various Airflows in C (PQ4 Package Only) Airflow-ft/min (m/sec) fCLKIN (MHz) TA with Heatsink* TA without Heatsink TA with Heatsink* Core 2X Bus Clock 25 33 40 25 33 40 16 25 33 40 16 25 33 40 20 25 20 25 0 (0) 71 67 63 70 65 61 71 62 55 48 69 60 52 42 58 51 56 48 200 (1.01) 76 74 71 73 68 65 76 71 66 62 72 64 57 51 68 64 61 55 400 (2.03) 79 77 75 75 72 69 79 75 71 68 75 68 63 58 73 70 66 61 600 (3.04) 79 77 75 75 72 69 79 75 71 68 75 68 63 58 73 70 66 61 800 (4.06) 80 79 77 76 74 71 80 77 74 72 76 71 66 62 76 73 68 64 1000 (5.07) 80 79 77 76 74 71 80 77 74 72 76 71 66 62 76 73 68 64 Core 1X Bus Clock TA without Heatsink TA with Heatsink* TA without Heatsink Core 3X Bus Clock *0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Table 15. 80960Hx 208-Pin PQ4 Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter 0 (0) 1 200 (1.01) 1 400 (2.03) 1 600 (3.07) 1 800 (4.06) 1 1000 (5.07) 1 JA JC 12 11 10 7 8 5 8 5 7 4 7 4 Junction-to-Case (Case measured as shown in Figure 5) Case-to-Ambient (No Heatsink) Case-to-Ambient (With Heatsink)* NOTES: 1. This table applies to 80960Hx PQ4 plugged into socket or soldered directly to board. 2. JA = JC + CA *0.285" high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Advance Information Datasheet 25 80960HA/HD/HT 3.4 Heat Sink Adhesives Intel recommends silicone-based adhesives to attach heat sinks to the PGA package. There is no particular recommendation concerning the PQ4 package. 3.5 PowerQuad4 Plastic Package The 80960Hx family is available in an improved version of the common 208-lead SQFP plastic package called the PowerQuad4* (PQ4). The PQ4 package dimensions and lead pitch are identical to the SQFP package and the former PQ2 package, so the PQ4 fits into the same board footprint. The advantage of the PQ4 package is the superior thermal conductivity that allows the plastic version of the 80960Hx to operate with the same 0-85C temperature specifications as the more expensive ceramic PGA package. The PQ4 package integrates a copper heat sink within the package to dissipate heat effectively. See Table 14 and Table 15. 3.6 Stepping Register Information The memory-mapped register at FF008710H contains the 80960Hx Device ID. The ID is identical to the ID obtained from a JTAG Query. Figure 6 defines the current 80960Hx Device IDs. The value for device identification is compliant with the IEEE 1149.1 specification and Intel standards. Table 16 describes the fields of the device ID. Figure 6. 80960Hx Device Identification Register Part Number Version VCC Product Type Gen Model Manufacturer ID 1 1 0001 00 0 010 0 0000 00 1 001 1 28 24 20 16 12 8 4 0 26 Advance Information Datasheet 80960HA/HD/HT Table 16. Fields of 80960Hx Device ID Field Version VCC Product Type Generation Type Model Manufacturer ID Value See Table 18 1 = 3.3 V device 00 0100 (Indicates i960 CPU) 0010 = H-series See Table 17 000 0000 1001 (Indicates Intel) Definition Indicates major stepping changes. Indicates that a device is 3.3 V. Designates type of product. Indicates the generation (or series) the product belongs to. Indicates member within a series and specific model information. Manufacturer ID assigned by IEEE. Table 17. 80960Hx Device ID Model Types Device 80960HA 80960HD 80960HT See Table 18 Version VCC 1 1 1 Product 000100 000100 000100 Gen. 0010 0010 0010 Model 00000 00001 00010 Manufacturer ID 00000001001 00000001001 00000001001 `1' 1 1 1 Table 18. Device ID Version Numbers for Different Steppings Stepping A0 A1 A2 B0, B2 This data sheet applies to the B2 stepping. Version 0000 0001 0001 0010 Advance Information Datasheet 27 80960HA/HD/HT 3.7 Sources for Accessories The following is a list of suggested sources for 80960Hx accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Sockets * 3M Textool Test and Interconnection Products 6801 River Place Blvd. MS 130-3N-29 Austin, TX 78726-9000 (800) 328-0411 FAX: (800) 932-9373 * Concept Mfg, Inc. (Decoupling Sockets) 400 Walnut St. Suite 609 Redwood City, CA 94063 (415) 365-1162 FAX: (415) 365-1164 Heatsinks/Fins * Thermalloy, Inc. 2021 West Valley View Lane Dallas, TX 75234-8993 (972) 243-4321 FAX: (972) 241-4656 * Wakefield Engineering, Inc. 60 Audubon Road Wakefield, MA 01880 (617) 245-5900 FAX: (617) 246-0874 * Aavid Thermal Technologies, Inc. One Kool Path Laconia, NH 03247-0400 (603) 523-3400 28 Advance Information Datasheet 80960HA/HD/HT 4.0 4.1 Electrical Specifications Absolute Maximum Ratings Parameter Storage Temperature Case Temperature Under Bias Supply Voltage with respect to VSS Voltage on VCC5 with respect to VSS Voltage on Other Pins with respect to VSS Maximum Rating -65 C to +150 C -65oC to +110oC -0.5 V to + 4.6 V -0.5 V to + 6.5 V -0.5 V to VCC5 + 0.5 V Notice: This document contains information on products in the sampling and initial production phases of development. It is valid for the devices indicated in the revision history. The specifications within this data sheet are subject to change without notice. Verify with your local Intel sales office that you have the latest data sheet before finalizing a design. Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Warning: 4.2 Operating Conditions Table 19. Operating Conditions Symbol VCC VCC5 fCLKIN 1xcore fCLKIN 2xcore fCLKIN 3xcore TC Supply Voltage Input Protection Bias Input Clock Frequency - 1x Core (80960HA) Input Clock Frequency - 2x Core (80960HD) Input Clock Frequency - 3x Core (80960HT) Case Temp Under Bias (PGA and PQ4 Packages) Parameter Min 3.15 3.15 16 16 16 0 Max 3.45 5.5 40 40 25 85 Units V V MHz MHz MHz o C Advance Information Datasheet 29 80960HA/HD/HT 4.3 Recommended Connections Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every 80960Hx-based circuit board should include power (VCC) and ground (VSS) planes for power distribution. Every VCC pin must be connected to the power plane; every VSS pin must be connected to the ground plane. Pins identified as "NC" --no connect pins--must not be connected in the system. Liberal decoupling capacitance should be placed near the 80960Hx. The processor can cause transient power surges when its output buffers transition, particularly when connected to large capacitive loads. Low inductance capacitors and interconnects are recommended for best high-frequency electrical performance. Inductance can be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages offer the lowest possible inductance. For reliable operation, always connect unused inputs to an appropriate signal level. In particular, any unused interrupt (XINT7:0, NMI) input should be connected to VCC through a pull-up resistor, as should BTERM if not used. Pull-up resistors should be in the range of 20 K for each pin tied high. If READY or HOLD are not used, the unused input should be connected to ground. N.C. pins must always remain unconnected. 4.4 VCC5 Pin Requirements (VDIFF) In mixed-voltage systems that drive 80960Hx processor inputs in excess of 3.3 V, the VCC5 pin must be connected to the system's 5 V supply. To limit current flow into the VCC5 pin, there is a limit to the voltage differential between the VCC5 pin and the other VCC pins. The voltage differential between the 80960Hx VCC5 pin and its 3.3 V VCC pins should never exceed 2.25 V. This limit applies to power-up, power-down, and steady-state operation. Table 20 outlines this requirement. Meeting this requirement ensures proper operation and guarantees that the current draw into the VCC5 pin does not exceed the ICC5 specification. If the voltage difference requirements cannot be met due to system design limitations, an alternate solution may be employed. As shown in Figure 7, a minimum of 100 series resistor may be used to limit the current into the VCC5 pin. This resistor ensures that current drawn by the VCC5 pin does not exceed the maximum rating for this pin. Figure 7. VCC5 Current-Limiting Resistor +5 V (0.25 V) 100 (5%, 0.5 W) VCC5 Pin This resistor is not necessary in systems that can guarantee the VDIFF specification. In 3.3 V-only systems and systems that drive 80960Hx pins from 3.3 V logic, connect the VCC5 pin directly to the 3.3 V VCC plane. Table 20. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) Sym VDIFF Parameter VCC5-VCC Difference Min Max 2.25 Units V Notes VCC5 input should not exceed VCC by more than 2.25 V during power-up and power-down, or during steady-state operation. 30 Advance Information Datasheet 80960HA/HD/HT 4.5 VCCPLL Pin Requirements If the voltage on the VCCPLL power supply pin exceeds the VCC pin voltage by 0.5 V at any time, including the power up and power down sequences, excessive currents can permanently damage on-chip electrostatic discharge (ESD) protection diodes. The damage can accumulate over multiple episodes. Pragmatically, this problem only occurs when the VCCPLL and VCC pins are driven by separate power supplies or voltage regulators. Applications that use one power supply for VCCPLL and VCC are not typically at risk. Verify that your application does not allow the VCCPLL voltage to exceed VCC by 0.5 V. The VCCPL low-pass filter recommended in the Developer's Manual does not promote this problem. Advance Information Datasheet 31 80960HA/HD/HT 4.6 DC Specifications Table 21. 80960Hx DC Characteristics (Sheet 1 of 2) Per the conditions described in Section 4.3, "Recommended Connections" on page 30. Symbol VIL VIH VOL VOL VOH Parameter Input Low Voltage Input High Voltage Output Low Voltage All outputs except FAIL Output Low Voltage FAIL pin Output High Voltage Input Leakage Current ILI Non-Test Inputs TDI, TMS, TRST and ONCE Output Leakage Current ILO Non-Test Outputs TDO pin 80960HA 25 33 40 ICC Active (Power Supply) 80960HD 32 50 66 80 80960HT 60 75 80960HA 25 33 40 ICC Active (Thermal) 80960HD 32 50 66 80 80960HT 60 75 80960HA 25 33 40 ICC Test (Reset Mode) 80960HD 32 50 66 80 80960HT 60 75 ICC Test (ONCE mode) 392 518 628 413 645 851 1034 752 938 330 436 528 382 595 785 955 702 878 25 mA (7) mA (7,8) mA (4,6) 1 5 579 765 927 631 985 1300 1578 1165 1455 mA (4,5) A A 0.45 VOUT VCC 0.45 VOUT VCC -1 1 -110 A A 0 VIN VCC VIN = 0 V 2.4 VCC - 0.2 Min - 0.3 2.0 Typ Max +0.8 VCC5 + 0.3 0.4 0.2 0.4 Units V V V V V V IOL = 3 mA IOL = 100 A IOL = 5 mA IOH = -3 mA IOH = -100 A Notes 32 Advance Information Datasheet 80960HA/HD/HT Table 21. 80960Hx DC Characteristics (Sheet 2 of 2) Per the conditions described in Section 4.3, "Recommended Connections" on page 30. Symbol ICC5 Current on the VCC5 Pin CIN Parameter 80960HA 80960HD 80960HT Input Capacitance for: PQ4 PGA Output Capacitance of each output pin I/O Pin Capacitance Internal Pull-Up Resistance for ONCE, TMS, TDI and TRST 30 65 12 12 12 12 100 pF pF pF pF k FC = 1 MHz (10) Min Typ Max 200 200 200 Units Notes A (9) COUT CI/O RPU FC = 1 MHz (3,10) FC = 1 MHz (10) NOTES: 1. ICC Maximum is measured at worst case frequency, VCC, and temperature, with device operating and outputs loaded to the test conditions described in Section 4.7.1, "AC Test Conditions" on page 37. 2. ICC Typical is not tested. 3. Output Capacitance is the capacitive load of a floating output. 4. Measured with device operating and outputs loaded to the test conditions in Figure 8 "AC Test Load" on page 37. Input signals rise to VCC and fall to VSS. 5. ICC Active (Power Supply) value is provided for selecting your system's power supply. It is measured using one of the worst case instruction mixes with VCC = 3.45 V. This parameter is characterized but not tested. 6. ICC Active (Thermal) value is provided for your system's thermal management. Typical ICC is measured with VCC = 3.3 V and temperature = 25C. This parameter is characterized but not tested. 7. ICC Test (Power modes) refers to the ICC values that are tested when the 80960HA/HD/HT is in Reset mode or ONCE mode with VCC = 3.45 V. 8. Worst case is VCC = 3.45 V, 0C. 9. ICC5 is tested at VCC = 3.0 V, VCC5 = 5.25 V. 10.Pin capacitance is characterized, but not tested. Advance Information Datasheet 33 80960HA/HD/HT 4.7 AC Specifications Table 22. 80960Hx AC Characteristics (Sheet 1 of 2) Per conditions in Section 4.2, "Operating Conditions" on page 29 and Section 4.7.1, "AC Test Conditions" on page 37. Symbol Parameter Input Clock (1,7) CLKIN Frequency TF Min Max Units Notes 80960HA 80960HD 80960HT 80960HA 80960HD 80960HT 16 16 16 25 25 40 -250 8 40 40 25 62.5 62.5 62.5 +250 MHz MHz MHz ns ns ns ps ns ns ns ns (11) (11) (11) (11) (11) CLKIN Period T TCS TCH CLKIN Period Stability CLKIN High Time CLKIN Low Time 80960HA 80960HD 80960HT TCL 8 8 8 0 0 4 4 TCR TCF CLKIN Rise Time CLKIN Fall Time ns ns Synchronous Outputs (1,2,3,6) Output Valid Delay and Output Hold for all outputs except DT/R, BLAST and BREQ for 3.3 V and 5 V inputs and I/Os. Output Valid Delay and Output Hold for DT/R TOV2, TOH2 TOV1, TOH1 1.5 9.5 ns 80960HA 80960HD 80960HT Output Valid Delay and Output Hold for BLAST Output Valid Delay and Output Hold for BREQ Output Valid Delay and Output Hold for A3:2 Output Float for all outputs T/2 + 1.5 3T/4 + 1.5 5T/6 + 1.5 1.5 0.5 1.5 1.5 T/2 + 9.5 3T/4 + 9.5 5T/6 + 9.5 9 9 8.5 9 ns ns ns ns ns TOV3, TOH3 TOV4, TOH4 TOV5, TOH5 TOF ns (11) Synchronous Inputs (1,7,8,9) TIS1 Input Setup for all inputs except READY, BTERM, HOLD, and BOFF Input Hold for all inputs except READY, BTERM, 2.5 2.5 6 ns ns ns TIH1 HOLD, and BOFF Input Setup for READY, BTERM, HOLD, and TIS2 BOFF NOTE: See Table 23 "AC Characteristics Notes" on page 36 for all notes related to AC specifications. 34 Advance Information Datasheet 80960HA/HD/HT Table 22. 80960Hx AC Characteristics (Sheet 2 of 2) Per conditions in Section 4.2, "Operating Conditions" on page 29 and Section 4.7.1, "AC Test Conditions" on page 37. Symbol TIH2 Parameter Input Hold for READY, BTERM, HOLD, and Min 2.5 Max Units ns Notes BOFF Relative Output Timings (1,2,3,6,10) TAVSH1 TAVSH2 TAVEL1 TAVEL2 TNLQV TDVNH TNLNH TNHQX TEHTV A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C Valid to ADS Rising A31:2 Valid to DEN Falling BE3:0, W/R, SUP Valid to DEN Falling WAIT Falling to Output Data Valid Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising Output Data Hold after WAIT Rising DT/R Hold after DEN High DT/R Valid to DEN Falling T-5 T-5 T-5 T-5 -5 -5 + N*T -4 + N*T -5 + (N+1)*T T/2 - 5 T+5 T+5 T+5 T+5 5 5 + N*T 4 + N*T 5 + (N+1)*T Infinite ns ns ns ns ns ns ns ns ns (10) (10) (10) (10) (10) (4,10) (4,10) (5,10) (10) TTVEL 80960HA 80960HD 80960HT T/2 - 4 T/4 - 4 T/6 - 4 ns ns ns (10) Relative Input Timings (1,7,10) TIS7 TIH7 TIS8 TIH8 XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold RESET Input Setup RESET Input Hold 6 2.5 3 T/4 + 1 ns ns ns ns (9) (9) (8) (8) NOTE: See Table 23 "AC Characteristics Notes" on page 36 for all notes related to AC specifications. Advance Information Datasheet 35 80960HA/HD/HT Table 23. AC Characteristics Notes NOTES: 1. See Section 4.8, "AC Timing Waveforms" on page 38 for waveforms and definitions. 2. See Figure 25 "Output Delay or Hold vs. Load Capacitance" on page 44 for capacitive derating information for output delays and hold times. 3. See Figure 22 "Rise and Fall Time Derating at 85C and Minimum VCC" on page 43 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 5. N = Number of wait states inserted with READY. 6. These specifications are guaranteed by the processor. 7. These specifications must be met by the system for proper operation of the processor. 8. RESET is an asynchronous input that has no required setup and hold time for proper operation. However, to guarantee the device exits the reset mode synchronized to a particular clock edge, the rising edge of RESET must meet setup and hold times to the rising edge of the CLKIN. 9. The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every clock and must be active for at least two consecutive CLKIN rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met. 10.Relative Output timings are not tested. 11.Not tested. 12.The processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for the following signals: A31:4, SUP, CT3:0, D/C, LOCK, W/R, BE3:0. Table 24. 80960Hx Boundary Scan Test Signal Timings Symbol TBSF TBSC TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSOV1 TBSOF1 TBSOV2 TBSOF2 TBSIS2 TBSIH2 Parameter TCK Frequency TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK -- TDI, TMS Input Hold from TCK -- TDI, TMS TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay Input Setup to TCK - All Inputs (Non-Test) Input Hold from TCK - All Inputs (Non-Test) 8 10 3 8 10 3 30 36 30 36 Min 0 125 40 40 8 8 Max 8 Infinite Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns (1) Relative to TCK Relative to TCK (1) Measured at 1.5 V (1) Measured at 1.5 V (1) 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1) Notes NOTE: 1. Not tested. 36 Advance Information Datasheet 80960HA/HD/HT 4.7.1 AC Test Conditions AC values are derived using the 50 pF load shown in Figure 8. Figure 25 "Output Delay or Hold vs. Load Capacitance" on page 44, shows how timings vary with load capacitance. Input waveforms (except for CLKIN) are assumed to have a rise and fall time of 2 ns from 0.8 V to 2.0 V. Figure 8. AC Test Load Output Pin CL CL = 50 pF for all signals Advance Information Datasheet 37 80960HA/HD/HT 4.8 AC Timing Waveforms Figure 9. CLKIN Waveform TCR TCF 2.0 V 1.5 V 0.8 V TCH TCL T Figure 10. Output Delay Waveform CLKIN 1.5 V 1.5 V Outputs: A31:2, D31:0 write only, DP3:0 write only PCHK, BE3:0, W/R, D/C, SUP, ADS, DEN, LOCK, HOLDA, BREQ, BSTALL, CT3:0, FAIL, WAIT, BLAST TOH1 1.5 V TOV1 Min Max 1.5 V Figure 11. Output Delay Waveform CLKIN 1.5 V 1.5 V TOV2 TOH2 DT/R 1.5 V Min Max 1.5 V 38 Advance Information Datasheet 80960HA/HD/HT Figure 12. Output Float Waveform CLKIN 1.5 V 1.5 V Outputs: A31:2, D31:0 write only, DP3:0 write only PCHK, BE3:0, W/R, D/C, SUP, ADS, DEN, LOCK, HOLDA, CT3:0, WAIT, BLAST, DT/R TOF Min Max Figure 13. Input Setup and Hold Waveform CLKIN 1.5 V 1.5 V TIH Min Valid 1.5 V TIS Min Inputs: READY, HOLD, BTERM, BOFF, D31:0 on reads, DP3:0 on reads, RESET Figure 14. NMI, XINT7:0 Input Setup and Hold Waveform A CLKIN 1.5 V TIS Min NMI, XINT7:0 B 1.5 V TIH Min A 1.5 V 1.5 V Valid 1.5 V NOTE: A and B edges are established by de-assertion of RESET. See Figure 29 "Cold Reset Waveform" on page 46. Advance Information Datasheet 39 80960HA/HD/HT Figure 15. Hold Acknowledge Timings CLKIN 1.5 V 1.5 V 1.5 V TIH Min HOLD 1.5 V TIS Min TIH Min TIS Min 1.5 V TOV1 TOH1 1.5 V Min 1.5 V 1.5 V TOV1 TOH1 Min Max Max HOLDA 1.5 V TOV TOH -- OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (TOV). The minimum output delay is referred to as the Output Hold (TOH). TIS TIH -- INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. Figure 16. Bus Backoff (BOFF) Timings CLKIN 1.5 V 1.5 V 1.5 V TIH TIS TIH TIS BOFF 1.5 V 1.5 V 1.5 V 40 Advance Information Datasheet 80960HA/HD/HT Figure 17. TCK Waveform TBSCR TBSCF 2.0 V 1.5 V 0.8 V TBSCH TBSCL TBSC Figure 18. Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 TCLK 1.5 V 1.5 V TBSIH1 1.5 V TBSIS1 Inputs: TMS TDI 1.5 V Valid 1.5 V Advance Information Datasheet 41 80960HA/HD/HT Figure 19. Output Delay and Output Float for TBSOV1 and TBSOF1 TCK 1.5 V 1.5 V 1.5 V TBSOV1 TBSOF1 TDO 1.5 V Valid Figure 20. Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 TCK 1.5 V 1.5 V 1.5 V TBSOV2 TBSOF2 Non-Test Outputs 1.5 V Valid Figure 21. Input Setup and Hold Waveform for TBSIS2 and TBSIH2 TCK 1.5 V 1.5 V 1.5 V TBSIS2 TBSIH2 Non-Test Inputs 1.5 V Valid 1.5 V 42 Advance Information Datasheet 80960HA/HD/HT Figure 22. Rise and Fall Time Derating at 85C and Minimum VCC 5 4 Time (ns) 3 2.0 to 0.8 V 0.8 to 2.0 V 2 1 50pF 100pF CL (pF) 150pF Figure 23. ICC Active (Power Supply) vs. Frequency 1800 ICC Active (Power Supply) (mA) 1600 1400 1200 1000 800 600 400 HA HD HT 200 0 0 10 20 30 40 CLKIN Frequency (MHz) Advance Information Datasheet 43 80960HA/HD/HT Figure 24. ICC Active (Thermal) vs. Frequency 1400 1200 ICC Active (Thermal) (mA) 1000 800 HA 600 HD 400 200 HT 10 20 30 40 CLKIN Frequency (MHz) Figure 25. Output Delay or Hold vs. Load Capacitance Output Valid Delays (ns) @ 1.5 V nom + 10 5.5 V Input Signals 3.3 V Input Signals nom + 5 nom 50 100 CL (pF) 150 44 Advance Information Datasheet 80960HA/HD/HT Figure 26. Output Delay vs. Temperature Processor Case Temperature (C) Output Valid Delays (ns) @ 1.5 V nom - 0.0 nom - 0.1 nom - 0.2 nom - 0.3 nom - 0.4 nom - 0.5 0C 85C Figure 27. Output Hold Times vs. Temperature Processor Case Temperature (C) Output Hold Times (ns) @ 1.5 V nom + 0.5 nom + 0.4 nom + 0.3 nom + 0.2 nom + 0.1 nom + 0 0C 85C Figure 28. Output Delay vs. VCC Output Valid or Hold Delays (ns) @ 1.5 V nom + 0.5 nom + 0.3 nom + 0.1 -nom + 0.1 -nom + 0.3 -nom + 0.5 3.15 3.45 VCC (volts) Advance Information Datasheet 45 CLKIN Figure 29. Cold Reset Waveform Bus Waveforms VCC, VCC5, ONCE CT3:0, ADS, LOCK, WAIT, DEN, BLAST W/R, DT/R, BREQ, FAIL, BSTALL D31:0, DP3:0 Inputs RESET CLKIN and VCC Stable to RESET high, minimum 10,000 CLKIN periods for PLL stabilization. NOTE: RESET high to First Bus Activity, HA=67, HD=34, HT=23 CLKIN periods Advance Information Datasheet STEST VCC stable: As specified in Table 20 "VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)" on page 30 Tsetup 1CLKIN Thold 1CLKIN Valid A31:2, SUP D/C, BE3:0 ~ ~ 46 A B A B Invalid 5.0 80960HA/HD/HT SUP, A31:2, D/C, BE3:0 D31:0, DP3:0 Maximum RESET Low to RESET State 16 CLKIN Periods RESET RESET High to First Bus Activity, HA=67, HD=34, HT=23 CLKIN Periods Minimum RESET Low Time 16 CLKIN Periods Tsetup 1 CLKIN Thold 1 CLKIN STEST Valid Advance Information Datasheet Figure 30. Warm Reset Waveform CLKIN ADS, LOCK, WAIT, DEN, BLAST, W/R, BREQ, FAIL, BSTALL DT/R 80960HA/HD/HT 47 Figure 31. Entering ONCE Mode VCC, VCC5 ADS, BE3:0, A31:2, D31:0, LOCK, WAIT, BLAST,W/R, D/C, DEN, DT/R, HOLDA, BLAST, FAIL, SUP,BREQ, CT3:0, BSTALL, DP3:0, PCHK ONCE mode is entered within 1 CLKIN period after ONCE becomes low while RESET is low. CLKIN and VCC Stable and RESET low and ONCE low to RESET high, minimum 10,000 CLKIN Periods. Advance Information Datasheet ONCE RESET NOTES: 1. ONCE mode may be entered prior to the rising edge of RESET: ONCE input is not latched until the rising edge of RESET. 2. The ONCE input may be removed after the processor enters ONCE mode. CLKIN 48 CLKIN may neither float nor remain idle. It must continue to run. 80960HA/HD/HT 80960HA/HD/HT Figure 32. Non-Burst, Non-Pipelined Requests without Wait States PMCON Function Bit Value External Ready Control 29 PipeLining 24 OFF 0 Bus Width 23-22 X xx Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 NXDA 19-16 0 0000 NWDD 15-14 0 00 NWAD 12-8 0 00000 NRDD 7-6 0 00 NRAD 4-0 0 00000 Disabled Disabled 0 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN D A D A D ADS A31:2, SUP, D/C, BE3:0, LOCK, CT3:0 W/R Valid Valid Valid BLAST DT/R DEN WAIT D31:0, DP3:0 PCHK In Out In Advance Information Datasheet 49 80960HA/HD/HT Figure 33. Non-Burst, Non-Pipelined Read Request with Wait States PMCON Function Bit Value External Ready Control 29 PipeLining 24 OFF 0 Bus Width 23-22 X xx Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 NXDA 19-16 1 0001 NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 X xx NRAD 4-0 3 00011 Disabled Disabled 0 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN 3 2 1 D 1 A ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN D/C, SUP, LOCK, CT3:0 Valid WAIT D31:0, DP3:0 In PCHK 50 Advance Information Datasheet 80960HA/HD/HT Figure 34. Non-Burst, Non-Pipelined Write Request with Wait States PMCON Function Bit Value External Ready Control 29 Burst 28 PipeLining 24 OFF 0 Bus Width 23-22 X xx Odd Parity 21 X x Parity Enable 20 Enabled 1 NXDA 19-16 1 0001 NWDD 15-14 X xxxxx NWAD 12-8 3 00011 NRDD 7-6 X xx NRAD 4-0 X xxxxx Disabled Disabled 0 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN 3 2 1 D 1 A ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN D/C, SUP, LOCK, CT3:0 Valid WAIT D31:0, DP3:0 Out PCHK Advance Information Datasheet 51 80960HA/HD/HT Figure 35. Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus PMCON Function Bit Value External Ready Control 29 Burst 28 PipeLining 24 OFF 0 Bus Width 23-22 32-Bit 10 Odd Parity 21 X x Parity Enable 20 Enabled 1 NXDA 19-16 0 0000 NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 0 00 NRAD 4-0 0 00000 Disabled Enabled 1 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN D D D D A ADS A31:4, SUP, CT3:0,D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0, DP3:0 In0 In1 In2 In3 PCHK 52 Advance Information Datasheet 80960HA/HD/HT Figure 36. Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus PMCON Function Bit Value External Ready Control 29 PipeLining 24 OFF 0 Bus Width 23-22 32-Bit 10 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 NXDA 19-16 1 0001 NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 1 01 NRAD 4-0 2 00010 Disabled Enabled 1 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN 2 1 D 1 D 1 D 1 D 1 A ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0, DP3:0 In0 In1 In2 In3 PCHK Advance Information Datasheet 53 80960HA/HD/HT Figure 37. Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus PMCON External Function Ready Control 29 PipeLining 24 OFF 0 Bus Width 23-22 32-Bit 10 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 NXDA 19-16 0 0000 NWDD 15-14 0 00 NWAD 12-8 0 00000 NRDD 7-6 X xx NRAD 4-0 X xxxxx Bit Value Disabled Enabled 1 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN D D D D A ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0, DP3:0 Out0 Out1 Out2 Out3 PCHK 54 Advance Information Datasheet 80960HA/HD/HT Figure 38. Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus PMCON Function Bit Value External Ready Control 29 Burst 28 PipeLining 24 OFF 0 Bus Width 23-22 32-bit 10 Odd Parity 21 X x Parity Enable 20 Enabled 1 NXDA 19-16 1 0001 NWDD 15-14 1 01 NWAD 12-8 2 00010 NRDD 7-6 X xx NRAD 4-0 X xxxxx Disabled Enabled 1 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN 2 1 D 1 D 1 D 1 D 1 A ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0, DP3:0 Out0 Out1 Out2 Out3 PCHK Advance Information Datasheet 55 80960HA/HD/HT Figure 39. Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus PMCON Function Bit Value External Ready Control 29 PipeLining 24 OFF 0 Bus Width 23-22 16-Bit 01 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 NXDA 19-16 1 0001 NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 1 01 NRAD 4-0 2 00010 Disabled Enabled 1 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN 2 1 D 1 D 1 D 1 D 1 A ADS SUP, CT3:0, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE W/R Valid BLAST DT/R DEN A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 BE1/A1 WAIT D31:0, DP3:0 PCHK D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 56 Advance Information Datasheet 80960HA/HD/HT Figure 40. Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus PMCON Function Bit Value External Ready Control 29 PipeLining 24 OFF 0 Bus Width 23-22 8-Bit 00 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 NXDA 19-16 1 0001 NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 1 01 NRAD 4-0 2 00010 Disabled Enabled 1 0 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. A CLKIN 2 1 D 1 D 1 D 1 D 1 A ADS SUP, CT3:0, D/C, LOCK, A31:4 Valid W/R BLAST DT/R DEN A3:2 A3:2 = 00, 01, 10 or 11 BE1/A1, BE0/A0 A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11 WAIT D31:0, DP3:0 PCHK D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 Advance Information Datasheet 57 80960HA/HD/HT Figure 41. Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control 29 X x PipeLining 24 ON 1 Bus Width 23-22 32-Bit 10 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 Disabled 0 NXDA 19-16 X xxxx NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 X xx NRAD 4-0 0 00000 Bit Value NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1 CLKIN A A' D A'' D' A''' D'' A'''' D''' D'''' 2 ADS A31:4, SUP, CT3:0, D/C, LOCK Valid Valid Valid Valid Valid Invalid W/R Invalid A3:2 BE3:0 D31:0, DP3:0 Valid Valid Valid Valid Valid Invalid IN D IN D' IN D'' IN D''' IN D'''' WAIT BLAST DT/R DEN PCHK 1. Non-pipelined request concludes, pipelined reads begin. 2. Pipelined reads conclude, non-pipelined requests begin. 58 Advance Information Datasheet 80960HA/HD/HT Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus PMCON External Function Ready Control 29 X x PipeLining 24 ON 1 Bus Width 23-22 32-Bit 10 Parity Enable 20 Enabled 1 Burst 28 Disabled 0 Odd Parity 21 X x NXDA 19-16 X xxxx NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 X xx NRAD 4-0 1 00001 Bit Value NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1 CLKIN A 1 A' D 1 D' 2 ADS A31:4, SUP, CT3:0, D/C, LOCK Valid Valid Invalid W/R Invalid A3:2 BE3:0 D31:0, DP3:0 Valid Valid Invalid IN D IN D' WAIT BLAST DT/R DEN PCHK 1. Non-pipelined request concludes, pipelined reads begin 2. Pipelined reads conclude, non-pipelined requests begin Advance Information Datasheet 59 80960HA/HD/HT Figure 43. Burst, Pipelined Read Request without Wait States, 32-Bit Bus PMCON External Function Ready Control 29 X x PipeLining 24 ON 1 Bus Width 23-22 32-Bit 10 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 Enabled 1 NXDA 19-16 X xxxx NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 0 00 NRAD 4-0 0 00000 Bit Value NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1A CLKIN D D D A' D D' D' 2 ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK Valid Valid InValid W/R A3:2 00 01 10 11 Valid Valid InValid D31:0, DP3:0 IN D IN D IN D IN D IN D IN D WAIT BLAST DT/R DEN PCHK 1. Non-pipelined request concludes, pipelined reads begin 2. Pipelined reads conclude, non-pipelined requests begin 60 Advance Information Datasheet 80960HA/HD/HT Figure 44. Burst, Pipelined Read Request with Wait States, 32-Bit Bus PMCON Function Bit Value External Ready Control 29 X x PipeLining 24 ON 1 Bus Width 23-22 32-Bit 10 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 Enabled 1 NXDA 19-16 X xxxx NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 1 01 NRAD 4-0 2 00010 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 2 1 D 1 D 1 1A CLKIN D 1 A' D 2 1 D' 2 ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R Valid Valid Invalid Invalid Invalid A3:2 00 01 10 11 Valid D31:0, DP3:0 IN D IN D IN D IN D IN D' WAIT BLAST DT/R DEN PCHK 1. Non-pipelined request concludes, pipelined reads begin. 2. Pipelined reads conclude, non-pipelined requests begin. Advance Information Datasheet 61 80960HA/HD/HT Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus PMCON Function Bit Value External Ready Control 29 X x Burst 28 Enabled 1 PipeLining 24 ON 1 Bus Width 23-22 8-Bit 00 Odd Parity 21 X x Parity Enable 20 Enabled 1 NRDD 7-6 1 01 NXDA 19-16 X xxxx NWDD 15-14 X xx NWAD 12-8 X xxxxx NRAD 4-0 2 00010 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 2 1 D 1 D 1 D 1A 1 A' D 2 1 D' 2 CLKIN ADS A31:4, SUP, CT3:0, D/C, LOCK W/R Valid Valid Invalid Invalid Invalid Invalid D7:0 D' A3:2 A3:2 = 00, 01, 10, or 11 Valid BE1/A1, BE0/A0 D31:0, DP3:0 A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 = 11 Valid D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 WAIT BLAST DT/R DEN PCHK 1. Non-pipelined request concludes, pipelined reads begin 2. Pipelined reads conclude, non-pipelined requests begin 62 Advance Information Datasheet 80960HA/HD/HT Figure 46. Burst, Pipelined Read Request with Wait States, 16-Bit Bus PMCON Function Bit Value External Ready Control 29 X x PipeLining 24 ON 1 Bus Width 23-22 16-Bit 01 Odd Parity 21 X x Parity Enable 20 Enabled 1 Burst 28 Enabled 1 NXDA 19-16 X xxxx NWDD 15-14 X xx NWAD 12-8 X xxxxx NRDD 7-6 1 01 NRAD 4-0 2 00010 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 1 A CLKIN 2 1 D 1 D 1 D 1 A' D 2 2 1 D' ADS A31:4, SUP, CT3:0, D/C, BE0/BLC, BE3/BHE, LOCK W/R Valid Valid Invalid Invalid A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 Valid Invalid BE1/A1 Valid Invalid D31:0, DP3:0 WAIT D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 D15:0 D' BLAST DT/R DEN PCHK 1. Non-pipelined request concludes, pipelined reads begin 2. Pipelined reads conclude, non-pipelined requests begin Advance Information Datasheet 63 80960HA/HD/HT Figure 47. Using External READY Quad-Word Read Request NRAD = 0, NRDD = 0, NXDA = 0 Ready Enabled A1 D D D D CLKIN Quad-Word Write Request NWAD = 1, NWDD = 0, NWDA = 0 Ready Enabled 2 D 1 D 1 D A 1 1 D ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK Valid Valid W/R BLAST DT/R DEN READY BTERM A3:2 00 01 10 11 00 01 10 11 WAIT D31:0, DP3:0 PCHK D0 D1 D2 D3 D0 D1 D2 D3 NOTE: Pipelining must be disabled to use READY. 64 Advance Information Datasheet 80960HA/HD/HT Figure 48. Terminating a Burst with BTERM Quad-Word Read Request NRAD = 0, NRDD = 0, NRDA = 0 Ready Enabled A D 1 A D 1 A CLKIN D 1 D 1 ADS A31:4, SUP, CT3:0, D/C, BE3:0, LOCK W/R Valid BLAST DT/R DEN READY See Note BTERM A3:2 00 01 10 11 WAIT D31:0, DP3:0 PCHK Note: READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM signal terminates a bus access when the signal is asserted during the last (or only) data transfer of the bus access. D0 D1 D2 D3 Advance Information Datasheet 65 80960HA/HD/HT Figure 49. BREQ and BSTALL Operation CLKIN ADS BLAST BREQ BSTALL The processor can stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted). Depending on the instruction stream and memory wait states, the two signals can be separated by several CLKIN cycles. Bus arbitration logic that logically "ANDs" BSTALL and BREQ will not correctly grant the bus to the processor in all stall cases, potentially degrading processor performance. Do not logically "AND" BSTALL and BREQ together in arbitration logic. Instead, the simplest bus arbitration should logically "OR" BSTALL and BREQ to determine the processor's bus ownership requirements. More sophisticated arbitration should recognize the priority nature of these two signals. Using a traffic light analogy, BREQ is a "yellow light" warning of a possible processor stall and BSTALL is a "red light" indicating a stall in progress. 66 Advance Information Datasheet 80960HA/HD/HT Figure 50. BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle. A D BOFF Mode A CLKIN Regenerate ADS ADS Burst May Change BLAST Non-Burst READY BOFF Suspend Request A31:2, SUP, CT3:0, D/C, BE3:0, WAIT, DEN, DT/R DP3:0 & D31:0, (WRITES) Valid PCHK Begin Request BOFF may be asserted to suspend request BOFF may not be asserted Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0 Valid End Request BOFF may not be asserted Advance Information Datasheet Resume Request 67 80960HA/HD/HT Figure 51. HOLD Functional Timing Word Read Request NRAD=0, NXDA=0 Word Read Request NRAD=1, NXDA=1 Hold State Hold State CLKIN ADS A31:2, SUP, CT3:0, D/C, BE3:0, WAIT, DEN, DT/R Valid Valid BLAST LOCK HOLD HOLDA 68 Advance Information Datasheet 80960HA/HD/HT Figure 52. LOCK Delays HOLDA Timing CLKIN ADS W/R BLAST LOCK HOLD HOLDA Figure 53. FAIL Functional Timing RESET (Internal Self-Test) Pass (Bus Test) Pass ~ ~ 80960HA: 80960HD: 80960HT: 257,517 Cycles 128,761 Cycles 85,840 Cycles Fail 30 Cycles 15 Cycles 10 Cycles ~ ~ FAIL ~ ~ ~ ~ Fail 113 Cycles 94 Cycles 90 Cycles Advance Information Datasheet 69 80960HA/HD/HT Figure 54. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions Byte Offset 0 4 8 12 16 20 24 Word Offset 0 1 2 3 4 5 6 Short Request (Aligned) Short Requests (Unaligned) Short-Word Load/Store Short Request (Aligned) Byte, Byte Requests Word Request (Aligned) Trey, Byte, Requests Word Load/Store Short, Short Requests Byte, Trey, Requests One Double-Word Burst (Aligned) Trey, Byte, Trey, Byte, Requests Short, Short, Short, Short Requests Double-Word Load/Store Byte, Trey, Byte, Trey, Requests Word, Word Requests One Double-Word Request (Aligned) NOTES: 1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes adjacent requests to occur for full words to the same address. 70 Advance Information Datasheet 80960HA/HD/HT Figure 55. A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued) 0 Byte Offset 4 8 12 16 20 24 Word Offset 0 1 2 3 4 One Three-Word Request (Aligned) Trey, Byte, Trey, Byte, Trey, Byte Requests 5 6 Triple-Word Load/Store Short, Short, Short, Short Short, Short, Short Requests Byte, Trey, Byte, Trey, Byte, Trey Requests Word, Word, Word Requests Word, Word, Word Requests Word, Word, Word Requests One Four-Word Request (Aligned) Trey, Byte, Trey, Byte, Trey, Byte Trey, Byte Requests Quad-Word Load/Store 8 Short Requests Byte, Trey, Byte, Trey, Byte, Trey, Byte, Trey, Requests 4 Word Requests 4 Word Requests NOTES: 1. All requests that are less than a word in size and are cacheable will be promoted to a word to be cached. This causes adjacent requests to occur for full words to the same address. Advance Information Datasheet 71 80960HA/HD/HT Figure 56. A Summary of Aligned and Unaligned Transfers for 16-Bit Bus Byte Offset 0 4 8 12 16 20 24 Word Offset 0 1 Short 2 3 4 5 6 Short 16-Bit Bus Byte, Byte Short Byte, Byte Two Short Burst Byte, Short, Byte Word 16-Bit Bus (Short)*2 Byte, Short, Byte Two Short Burst Four Short Burst (Byte, Short, Byte) *2 Double Word 16-Bit Bus (Short) *4 (Byte, Short, Byte)*2 (Two Short Burst)*2 Four Short Burst Four Short Burst, Two Short Burst (Byte, Short, Byte) *3 Triple Word 16-Bit Bus (Short) *6 (Byte, Short, Byte) *3 (Two Short Burst) *3 (Two Short Burst) *3 (Four Short Burst)*2 (Byte, Short, Byte) *4 Quad Word 16-Bit Bus (Short) *8 (Byte, Short, Byte) *4 (Two Short Burst)*4 (Two Short Burst) *4 72 Advance Information Datasheet 80960HA/HD/HT Figure 57. A Summary of Aligned and Unaligned Transfers for 8-Bit Bus Byte Offset 0 4 8 12 16 20 24 Word Offset 0 1 Two Byte Burst 2 3 4 5 6 Short 8-Bit Bus Two Byte Burst Two Byte Burst Byte, Byte Four Byte Burst Three Byte Burst, Byte Word 8-Bit Bus (Two Byte Burst)*2 Byte, Three Byte Burst Four Byte Burst (Four Byte Burst) *2 (Three Byte Burst, Byte)*2 Double Word 8-Bit Bus (Two Byte Burst) *4 (Byte, Three Byte Burst) *2 (Four Byte Burst) *2 (Four Byte Burst) *2 (Four Byte Burst)*3 (Three Byte Burst, Byte)*3 Triple Word 8-Bit Bus (Two Byte Burst) *6 (Byte, Three Byte Burst) *3 (Four Byte Burst)*3 (Four Byte Burst)*3 (Four Byte Burst)*4 (Three Byte Burst, Byte)*4 Quad Word 16-Bit Bus (Two Byte Burst) *8 (Byte, Three Byte Burst) *4 (Four Byte Burst)*4 (Four Byte Burst) *4 Advance Information Datasheet 73 80960HA/HD/HT Figure 58. Idle Bus Operation Write Request NWAD=2, NXDA = 0 Ready Disabled Read Request NRAD=2, NXDA = 0 Ready Disabled Idle Bus (not in Hold Acknowledge state) CLKIN ADS A31:4, SUP, D/C, BE3:0, CT3:0 Valid Valid LOCK Valid Valid W/R BLAST DT/R DEN A3:2 Valid Valid WAIT D31:0 Out In READY, BTERM PCHK 74 Advance Information Datasheet 80960HA/HD/HT Figure 59. Bus States Tb BOFF BOFF !BOFF BOFF WdCNT > 1 WdCNT = 1 !BOFF and READY and !BLAST or !BOFF and BTERM and !BLAST or !BOFF and !HOLD and BLAST and REQUEST and NXDA = 0 READ and Nrdd > 0 or WRITE and Nwdd > 0 Tdw3 Ta !RESET and !HOLD and REQUEST !BOFF and READ and Nrad = 0 or !BOFF and WRITE and Nwad = 0 Td1 !BOFF and READ and Nrdd = 0 and !BLAST or !BOFF and WRITE and Nwdd = 0 and !BLAST or READY! READ and Nrad > 0 or WRITE and Nwad > 0 !BOFF and BLAST and Nxda > 0 WaCNT = 1 Taw2 Trw4 WaCNT > 1 !HOLD and WxCNT=1 and REQUEST WxCNT > 1 !BOFF and !HOLD and BLAST and Nxda = 0 and !REQUEST To RESET and !ONCE ONCE and RESET !HOLD and WxCNT=1 and !REQUEST HOLD HOLD WxCNT=1 and HOLD !BOFF and HOLD and BLAST and Nxda= 0 Ti Th !HOLD RESET KEY: To = ONCE Ti = IDLE Th = HOLD Ta = ADDRESS Td = DATA Tb = BOFF'ed Taw= address to data wait Tdw= data to data wait Tdw= data to address wait REQUEST= One or more requests in the bus queue. READ= The current access is a read. WRITE= The current access is a write. NOTE: 1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as long as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the subsequent read access is concurrent with the last data cycle of the access. Because External Ready Control is disabled for Read Pipelining, the address cycle occurs during BLAST. 2. WaCNT is decremented during Taw 3. WdCNT is decremented during Tdw 4. WxCNT is decremented during Trw Advance Information Datasheet 75 80960HA/HD/HT 5.1 80960Hx Boundary Scan Chain Table 25. 80960Hx Boundary Scan Chain (Sheet 1 of 4) # DP3 DP2 DP0 DP1 STEST FAILBAR Enable for FAILBAR, BSTALL and BREQ ONCEBAR BOFFBAR D0 D1 D2 D3 D4 D5 D6 D7 Enable for DP(3:0) and D(31:0) D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 BOUNDARY SCAN CELL CELL TYPE Bidirectional Bidirectional Bidirectional Bidirectional Input Output Control Input Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Control Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional COMMENT NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI. 2. All outputs are three-state. 3. In output and bidirectional signals, a logical "1" on the enable signal enables the output. A logical "0" three-states the output. 76 Advance Information Datasheet 80960HA/HD/HT Table 25. 80960Hx Boundary Scan Chain (Sheet 2 of 4) # D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 BTERMBAR RDYBAR HOLD HOLDA Enable for HOLDA control ADSBAR BE3BAR BE2BAR BE1BAR BE0BAR BLASTBAR DENBAR WRRDBAR DTRBAR Enable for DTRBAR WAITBAR BSTALL DATACODBAR USERSUPBAR Enable for ADSBAR, BEBAR, BLASTBAR, DENBAR, WRRDBAR, WAITBAR, DCBAR, SUPBAR and LOCKBAR, BOUNDARY SCAN CELL CELL TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Input Input Input Output Control Output Output Output Output Output Output Output Output Output Control Output Output Output Output Appears as DCBAR in BSDL file. Appears as SUPBAR in BSDL file. Appears as WRBAR in BSDL file. Appears as BEBAR(3:0) in BSDL file. Appears as READYBAR in BSDL file. COMMENT Control NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI. 2. All outputs are three-state. 3. In output and bidirectional signals, a logical "1" on the enable signal enables the output. A logical "0" three-states the output. Advance Information Datasheet 77 80960HA/HD/HT Table 25. 80960Hx Boundary Scan Chain (Sheet 3 of 4) # BOUNDARY SCAN CELL LOCKBAR BREQ A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 Enable for A(31:0) and CT(3:0) A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 NMIBAR CELL TYPE Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Control Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input COMMENT NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI. 2. All outputs are three-state. 3. In output and bidirectional signals, a logical "1" on the enable signal enables the output. A logical "0" three-states the output. 78 Advance Information Datasheet 80960HA/HD/HT Table 25. 80960Hx Boundary Scan Chain (Sheet 4 of 4) # BOUNDARY SCAN CELL XINT7BAR XINT6BAR XINT5BAR XINT4BAR XINT3BAR XINT2BAR XINT1BAR XINT0BAR RESETBAR CLKIN CT3 CT2 CT1 CT0 PCHK PCHK enable CELL TYPE Input Input Input Input Input Input Input Input Input Input Output Output Output Output Output Control Appears as PCHKBAR in BSDL file. Appears as CT(3:0) in BSDL file. COMMENT Appears as XINTBAR(7:0) in BSDL file. NOTES: 1. Cell#1 connects to TDO and cell #112 connects to TDI. 2. All outputs are three-state. 3. In output and bidirectional signals, a logical "1" on the enable signal enables the output. A logical "0" three-states the output. Advance Information Datasheet 79 80960HA/HD/HT 5.2 Boundary Scan Description Language Example Boundary-Scan Description Language (BSDL) example 14-2 meets the de facto standard means of describing essential features of ANSI/IEEE 1149.1-1993 compliant devices. Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 1 of 8) -- Copyright Intel Corp. 1995 - - *************************************************************************** - - Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. - - *************************************************************************** - - Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto standard means of describing essential features of ANSI/IEEE 1149.1-1990 compliant devices. This language is under consideration by the IEEE for formal inclusion within a supplement to the 1149.1-1990 standard. The generation of the supplement entails an extensive IEEE review and a formal acceptance balloting procedure which may change the resultant form of the language. Be aware that this process may extend well into 1993, and at this time the IEEE does not endorse or hold an opinion on the language. - - *************************************************************************** --- i960(R) Processor BSDL Model 80 Advance Information Datasheet 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 2 of 8) -- Project code HA -- File **NOT** verified electrically -- ------------------------------------------------- Rev 0.7 -- Rev 0.6 -- Rev 0.5 -- Rev 0.4 -- Rev 0.3 -- Rev 0.2 -- Rev 0.1 -- Rev 0.0 18 Dec 08 Dec 21 Nov 31 Oct 1995 1994 1994 1994 Updated for A-1 stepping. 26 July 1994 22 June 1994 16 Mar 30 Aug 1994 1993 entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= "PGA"); port (A ADSBAR BEBAR BLASTBAR BOFFBAR BREQ BSTALL BTERMBAR CT CLKIN D DENBAR DP DTRBAR DCBAR FAILBAR HOLD HOLDA LOCKBAR NMIBAR ONCEBAR PCHKBAR READYBAR RESETBAR STEST : out : out : out : out : in : out : out : in : out : in : inout : out : inout : out : out : out : in : out : out : in : in : out : in : in : in bit_vector(2 to 31); bit; bit_vector(0 to 3); bit; bit; bit; bit; bit; bit_vector(0 to 3); bit; bit_vector(0 to 31); bit; bit_vector(0 to 3); bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; Advance Information Datasheet 81 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 3 of 8) SUPBAR TCK TDI TDO TMS TRST WAITBAR WRBAR XINTBAR FIVEVREF VCCPLL VOLTDET VCC1 VCC2 VSS1 VSS2 NC : out : in : in : out : in : in : out : out : in bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 to 7); : linkage bit; : linkage bit; : out bit; : linkage bit_vector(0 to 23); : linkage bit_vector(0 to 20); : linkage bit_vector(0 to 25); : linkage bit_vector(0 to 22); : linkage bit_vector(0 to 4) ); use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PGA:PIN_MAP_STRING := "A " " " "ADSBAR "BEBAR "BLASTBAR "BOFFBAR "BREQ "BSTALL "BTERMBAR "CT "CLKIN : (D16, D17, E16, E17, F17, G16, G17, H17, J17,"& K17, L17, L16, M17, N17, N16, P17, Q17, P16,"& P15, Q16, R17, R16, Q15, S17, R15, S16, Q14, "& R14, Q13, S15), : R06,"& : (R09, S07, S06, S05),"& : S08,"& : B01,"& : R13,"& : R12,"& : R04,"& : (A11, A12, A13, A14),"& : C13,"& 82 Advance Information Datasheet 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 4 of 8) "D " " " "DENBAR "DP "DTRBAR "DCBAR "FAILBAR "HOLD "HOLDA "LOCKBAR "NMIBAR "ONCEBAR "PCHKBAR "READYBAR "RESETBAR "STEST "SUPBAR "TCK "TDI "TDO "TMS "TRST "WAITBAR "WRBAR " XINTBAR "FIVEVREF "VOLTDET "VCCPLL " VCC1 " " " VSS1 " " "NC : (E03, C02, D02, C01, E02, D01, F02, E01, F01,"& G01, H02, H01, J01, K01, L02, L01, M01, N01,"& N02, P01, P02, Q01, P03, Q02, R01, S01, Q03,"& R02, Q04, S02, Q05, R03),"& : S09,"& : (A03, B03, A04, B04),"& : S11,"& : S13,"& : A02,"& : R05,"& : S04,"& : S14,"& : D15,"& : C03,"& : B08,"& : S03,"& : A16,"& : B02,"& : Q12,"& : B05,"& : A07,"& : A08,"& : B06,"& : A06,"& : S12,"& : S10,"& : (B15, A15, A17, B16, C15, B17, C16, C17),"& : C05,"& : A05,"& : B10,"& : (M02, K02, J02, G02, N03, F03, C06, B07, B09, B11,"& B12, C14, E15, F16, H16, J16, K16, M16, N15, Q06,"& R07, R08, R10, R11),"& : (G03, H03, J03, K03, L03, M03, C07, C08, C09, C10,"& C11, C12, Q07, Q08, Q09, Q10, Q11, F15, G15, H15,"& J15, K15, L15, M15, A01, C04),"& : (A09, A10, B13, B14, D03)"; Advance Information Datasheet 83 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 5 of 8) attribute Tap_Scan_In attribute Tap_Scan_Mode attribute Tap_Scan_Out of of of TDI TMS TDO TRST TCK : signal is true; : signal is true; : signal is true; : signal is true; : signal is (66.0e6, BOTH); attribute Tap_Scan_Reset of attribute Tap_Scan_Clock of attribute Instruction_Length of Ha_Processor: entity is 4; attribute Instruction_Opcode of Ha_Processor: entity is "BYPASS "EXTEST "SAMPLE "IDCODE "RUBIST "CLAMP "HIGHZ "Reserved (1111)," & (0000)," & (0001)," & (0010)," & (0111)," & (0100)," & (1000)," & (1011, 1100)"; attribute Instruction_Capture of Ha_Processor: entity is "0001"; attribute Instruction_Private of Ha_Processor: entity is "Reserved" ; attribute Idcode_Register of Ha_Processor: entity is "0010" "1000100001000000" "00000001001" "1"; & & & --version, --part number --manufacturers identity --required by the standard attribute Register_Access of Ha_Processor: entity is "Runbist[32] "Bypass (RUBIST)," & (CLAMP, HIGHZ)"; {***************************************************************************} { { The first cell, cell 0, is closest to TDO BC_1:Control, Output3 CBSC_1:Bidir BC_4: Input, Clock } } {***************************************************************************} 84 Advance Information Datasheet 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 6 of 8) attribute Boundary_Cells of Ha_Processor: entity is "BC_4, BC_1, CBSC_1"; attribute Boundary_Length of Ha_Processor: entity is 112; attribute Boundary_Register of Ha_Processor: entity is "0 "1 "2 "3 "4 "5 "6 "7 "8 "9 (CBSC_1, (CBSC_1, (CBSC_1, (CBSC_1, (BC_4, (BC_1, (BC_1, (BC_4, (BC_4, (CBSC_1, DP(3), DP(2), DP(0), DP(1), STEST, FAILBAR, *, ONCEBAR, BOFFBAR, D(0), D(1), D(2), D(3), D(4), D(5), D(6), D(7), *, D(8), D(9), D(10), D(11), D(12), D(13), D(14), D(15), D(16), D(17), D(18), D(19), D(20), D(21), D(22), D(23), D(24), bidir, bidir, bidir, bidir, input, X, X, X, X, X)," 17, 1, 17, 1, 17, 1, 17, 1, & 6, & & & 17, 17, 17, 17, 17, 17, 17, 17, & 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, Z)," Z)," Z)," Z)," & & & & output3, X, control, 1)," input, input, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, X)," X)," X, X, X, X, X, X, X, X, Z)," & Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & "10 (CBSC_1, "11 (CBSC_1, "12 (CBSC_1, "13 (CBSC_1, "14 (CBSC_1, "15 (CBSC_1, "16 (CBSC_1, "17 (BC_1, "18 (CBSC_1, "19 (CBSC_1, "20 (CBSC_1, "21 (CBSC_1, "22 (CBSC_1, "23 (CBSC_1, "24 (CBSC_1, "25 (CBSC_1, "26 (CBSC_1, "27 (CBSC_1, "28 (CBSC_1, "29 (CBSC_1, "30 (CBSC_1, "31 (CBSC_1, "32 (CBSC_1, "33 (CBSC_1, "34 (CBSC_1, control, 1)," bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & & & & & & & & & 17, 1, Advance Information Datasheet 85 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 7 of 8) "35 (CBSC_1, "36 (CBSC_1, "37 (CBSC_1, "38 (CBSC_1, "39 (CBSC_1, "40 (CBSC_1, "41 (CBSC_1, "42 (BC_4, "43 (BC_4, "44 (BC_4, "45 (BC_1, "46 (BC_1, "47 (BC_1, "48 (BC_1, "49 (BC_1, "50 (BC_1, "51 (BC_1, "52 (BC_1, "53 (BC_1, "54 (BC_1, "55 (BC_1, "56 (BC_1, "57 (BC_1, "58 (BC_1, "59 (BC_1, "60 (BC_1, "61 (BC_1, "62 (BC_1, "63 (BC_1, "64 (BC_1, "65 (BC_1, "66 (BC_1, "67 (BC_1, "68 (BC_1, "69 (BC_1, "70 (BC_1, "71 (BC_1, "72 (BC_1, "73 (BC_1, D(25), D(26), D(27), D(28), D(29), D(30), D(31), BTERMBAR, READYBAR, HOLD, HOLDA, *, ADSBAR, BEBAR(3), BEBAR(2), BEBAR(1), BEBAR(0), BLASTBAR, DENBAR, WRBAR, DTRBAR, *, WAITBAR, BSTALL, DCBAR, SUPBAR, *, LOCKBAR, BREQ, A(31), A(30), A(29), A(28), A(27), A(26), A(25), A(24), A(23), A(22), bidir, bidir, bidir, bidir, bidir, bidir, bidir, input, input, input, X, X, X, X, X, X, X, X)," X)," X)," 17, 1, 17, 1, 17, 1, 17, 1, 17, 1, 17, 1, 17, 1, & & & 46, 1, & 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 56, 1, & 61, 1, 6, 1, Z)," Z)," Z)," Z)," & & & & Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & Z)," & Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & output3, X, control, 1)," output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, control, 1)," output3, X, output3, X, output3, X, output3, X, control, 1)," output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, X, output3, output3, X, X, 61, 1, 61, 1, & 61, 1, 6, 1, Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & & & & 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 86 Advance Information Datasheet 80960HA/HD/HT Example 1. Boundary-Scan Description Language (BSDL) for PGA Package Example (Sheet 8 of 8) "74 (BC_1, "75 (BC_1, "76 (BC_1, "77 (BC_1, "78 (BC_1, "79 (BC_1, "80 (BC_1, "81 (BC_1, "82 (BC_1, "83 (BC_1, "84 (BC_1, "85 (BC_1, "86 (BC_1, "87 (BC_1, "88 (BC_1, "89 (BC_1, "90 (BC_1, "91 (BC_1, "92 (BC_1, "93 (BC_1, "94 (BC_1, "95 (BC_4, "96 (BC_4, "97 (BC_4, "98 (BC_4, "99 (BC_4, "100(BC_4, "101(BC_4, "102(BC_4, "103(BC_4, "104(BC_4, "105(BC_4, "106(BC_1, "107(BC_1, "108(BC_1, "109(BC_1, "110(BC_1, "111(BC_1, end Ha_Processor; A(21), A(20), A(19), A(18), A(17), A(16), *, A(15), A(14), A(13), A(12), A(11), A(10), A(9), A(8), A(7), A(6), A(5), A(4), A(3), A(2), NMIBAR, XINTBAR(7), XINTBAR(6), XINTBAR(5), XINTBAR(4), XINTBAR(3), XINTBAR(2), XINTBAR(1), XINTBAR(0), RESETBAR, CLKIN, CT(3), CT(2), CT(1), CT(0), PCHKBAR, *, output3, output3, output3, output3, output3, output3, control, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, input, input, input, input, input, input, input, input, input, input, input, output3, output3, output3, output3, output3, control, X, X, X, X, X, X, 1)," X, X, X, X, X, X, X, X, X, X, X, X, X, X, X)," X)," X)," X)," X)," X)," X)," X)," X)," X)," X)," X, X, X, X, X, 1)"; 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, & 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, & & & & & & & & & & & 80, 1, Z)," & & & & & Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & & & & & & Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & 80, 1, Z)," 80, 1, Z)," 80, 1, Z)," 111, 1, Z)," Advance Information Datasheet 87 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 1 of 8) -- Copyright Intel Corporation 1995, 1996 -- ***************************************************************************** -- Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. -- ***************************************************************************** -- Boundary-Scan Description Language (BSDL Version 0.0) is a de-facto -- standard means of describing essential features of ANSI/IEEE 1149.1-1990 compliant devices. This language is under consideration by the IEEE for formal The generation of the inclusion within a supplement to the 1149.1-1990 standard. supplement entails an extensive IEEE review and a formal acceptance balloting procedure which may change the resultant form of the language. Be aware that this process may extend well into 1993, and at this time the IEEE does not endorse or hold an opinion on the language. -- i960(R) Processor BSDL Model -- Project code HA -- File **NOT** verified electrically -- ------------------------------------------------ Rev 0.8 -- Rev 0.7 -- Rev 0.6 -- Rev 0.5 -- Rev 0.4 -- Rev 0.3 -- Rev 0.2 -- Rev 0.1 -- Rev 0.0 4 Apr 18 Dec 08 Dec 21 Nov 31 Oct 1996 1995 1994 1994 1994 Changed for PQ2 Package Updated for A-1 stepping. 26 July 1994 22 June 1994 16 Mar 30 Aug 1994 1993 88 Advance Information Datasheet 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 2 of 8) entity Ha_Processor is generic(PHYSICAL_PIN_MAP : string:= "PQ2"); port (A ADSBAR BEBAR BLASTBAR BOFFBAR BREQ BSTALL BTERMBAR CT CLKIN D DENBAR DP DTRBAR DCBAR FAILBAR HOLD HOLDA LOCKBAR NMIBAR ONCEBAR PCHKBAR READYBAR RESETBAR STEST SUPBAR TCK TDI TDO TMS TRST WAITBAR WRBAR XINTBAR FIVEVREF VCCPLL : out : out : out : out : in : out : out : in : out : in : inout : out : inout : out : out : out : in : out : out : in : in : out : in : in : in : out : in : in : out : in : in : out : out : in bit_vector(2 to 31); bit; bit_vector(0 to 3); bit; bit; bit; bit; bit; bit_vector(0 to 3); bit; bit_vector(0 to 31); bit; bit_vector(0 to 3); bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit; bit_vector(0 to 7); : linkage bit; : linkage bit; Advance Information Datasheet 89 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 3 of 8) VCC1 VCC2 VSS1 VSS2 : linkage bit_vector(0 to 23); : linkage bit_vector(0 to 23); : linkage bit_vector(0 to 23); : linkage bit_vector(0 to 23) ); use STD_1149_1_1990.all; use i960ha_a.all; attribute PIN_MAP of Ha_Processor : entity is PHYSICAL_PIN_MAP; constant PQ2:PIN_MAP_STRING := "A " " "ADSBAR "BEBAR "BLASTBAR "BOFFBAR "BREQ "BSTALL "BTERMBAR "CT "CLKIN "D " " "DENBAR "DP "DTRBAR "DCBAR "FAILBAR "HOLD "HOLDA "LOCKBAR "NMIBAR : (151, 150, 147, 146, 145, 144, 141, 140, 139, 138,"& 135, 134, 133, 132, 127, 126, 125, 124, 121, 120,"& 119, 118, 113, 112, 111, 110, 107, 106, 105, 104),"& : 77,"& : (83, 82, 79, 78),"& : 84,"& : 10,"& : 100,"& : 91,"& : 67,"& : (183, 182, 181, 180),"& : 175,"& : (12, 13, 14, 15, 20, 21, 22, 23, 26, 27, 28, 29,"& 34, 35, 36, 37, 39, 40, 41, 42, 45, 50, 51, 52,"& 54, 55, 56, 57, 61, 62, 63, 64),"& : 85,"& : (206, 207, 203, 202),"& : 89,"& : 96,"& : 5,"& : 69,"& : 72,"& : 99,"& : 159,"& 90 Advance Information Datasheet 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 4 of 8) "ONCEBAR "PCHKBAR "READYBAR "RESETBAR "STEST "SUPBAR "TCK "TDI "TDO "TMS "TRST "WAITBAR "WRBAR "XINTBAR "FIVEVREF "VCCPLL "VCC1 " "VCC2 " " "VSS1 " "VSS2 " " : 6,"& : 189,"& : 68,"& : 174,"& : 208,"& : 97,"& : 194,"& : 191,"& : 188,"& : 192,"& : 193,"& : 90,"& : 88,"& : (169, 168, 167, 166, 163, 162, 161, 160),"& : 197,"& : 177,"& : (1, 4, 9, 11, 17, 19, 25, 31, 33, 38, 44, 46,"& 49, 59, 60, 66, 71, 74, 76, 81, 87, 92, 95, 101),"& : (102, 109, 115, 117, 123, 128, 131, 137, 143, 149,"& 153, 154, 158, 165, 171, 173, 176, 179, 185, 187,"& 196, 199, 201, 204),"& : (2, 3, 7, 8, 16, 18, 24, 30, 32, 43, 47, 48,"& 53, 58, 65, 70, 73, 75, 80, 86, 93, 94, 98, 103),"& : (108, 114, 116, 122, 129, 130, 136, 142, 148, 152,"& 155, 156, 157, 164, 170, 172, 178, 184, 186, 190,"& 195, 198, 200, 205)"; attribute Tap_Scan_In attribute Tap_Scan_Mode attribute Tap_Scan_Out of of of TDI TMS TDO TRST TCK : signal is true; : signal is true; : signal is true; : signal is true; : signal is (66.0e6, BOTH); attribute Tap_Scan_Reset of attribute Tap_Scan_Clock of attribute Instruction_Length of Ha_Processor: entity is 4; attribute Instruction_Opcode of Ha_Processor: entity is Advance Information Datasheet 91 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 5 of 8) "BYPASS "EXTEST "SAMPLE "IDCODE "RUBIST "CLAMP "HIGHZ "Reserved (1111)," & (0000)," & (0001)," & (0010)," & (0111)," & (0100)," & (1000)," & (1011, 1100)"; attribute Instruction_Capture of Ha_Processor: entity is "0001"; attribute Instruction_Private of Ha_Processor: entity is "Reserved" ; attribute Idcode_Register of Ha_Processor: entity is "0001" & version, & part number "1000100001000000" "00000001001"& "1"; manufacturers identity required by the standard attribute Register_Access of Ha_Processor: entity is "Runbist[32] "Bypass (RUBIST)," & (CLAMP, HIGHZ)"; ******************************************************************************* { { The first cell, cell 0, is closest to TDO BC_1:Control, Output3 CBSC_1:Bidir BC_4: Input, Clock } } ******************************************************************************* attribute Boundary_Cells of Ha_Processor: entity is "BC_4, BC_1, CBSC_1"; attribute Boundary_Length of Ha_Processor: entity is 112; attribute Boundary_Register of Ha_Processor: entity is "0 "1 "2 "3 "4 "5 (CBSC_1, (CBSC_1, (CBSC_1, (CBSC_1, (BC_4, (BC_1, DP(3), DP(2), DP(0), DP(1), STEST, FAILBAR, bidir, bidir, bidir, bidir, input, X, X, X, X, X)," 17, 1, 17, 1, 17, 1, 17, 1, & 6, 1, Z)," Z)," Z)," Z)," & & & & output3, X, Z)," & 92 Advance Information Datasheet 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 6 of 8) "6 "7 "8 "9 (BC_1, (BC_4, (BC_4, (CBSC_1, *, ONCEBAR, BOFFBAR, D(0), D(1), D(2), D(3), D(4), D(5), D(6), D(7), *, D(8), D(9), D(10), D(11), D(12), D(13), D(14), D(15), D(16), D(17), D(18), D(19), D(20), D(21), D(22), D(23), D(24), D(25), D(26), D(27), D(28), D(29), D(30), control, 1)," input, input, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, X)," X)," X, X, X, X, X, X, X, X, & & & 17, 17, 17, 17, 17, 17, 17, 17, & 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & & & & & & & & & & & & & & & 1, 1, 1, 1, 1, 1, 1, 1, Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & "10 (CBSC_1, "11 (CBSC_1, "12 (CBSC_1, "13 (CBSC_1, "14 (CBSC_1, "15 (CBSC_1, "16 (CBSC_1, "17 (BC_1, "18 (CBSC_1, "19 (CBSC_1, "20 (CBSC_1, "21 (CBSC_1, "22 (CBSC_1, "23 (CBSC_1, "24 (CBSC_1, "25 (CBSC_1, "26 (CBSC_1, "27 (CBSC_1, "28 (CBSC_1, "29 (CBSC_1, "30 (CBSC_1, "31 (CBSC_1, "32 (CBSC_1, "33 (CBSC_1, "34 (CBSC_1, "35 (CBSC_1, "36 (CBSC_1, "37 (CBSC_1, "38 (CBSC_1, "39 (CBSC_1, "40 (CBSC_1, control, 1)," bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, bidir, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, X, Advance Information Datasheet 93 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 7 of 8) "41 (CBSC_1, "42 (BC_4, "43 (BC_4, "44 (BC_4, "45 (BC_1, "46 (BC_1, "47 (BC_1, "48 (BC_1, "49 (BC_1, "50 (BC_1, "51 (BC_1, "52 (BC_1, "53 (BC_1, "54 (BC_1, "55 (BC_1, "56 (BC_1, "57 (BC_1, "58 (BC_1, "59 (BC_1, "60 (BC_1, "61 (BC_1, "62 (BC_1, "63 (BC_1, "64 (BC_1, "65 (BC_1, "66 (BC_1, "67 (BC_1, "68 (BC_1, "69 (BC_1, "70 (BC_1, "71 (BC_1, "72 (BC_1, "73 (BC_1, "74 (BC_1, "75 (BC_1, D(31), BTERMBAR, READYBAR, HOLD, HOLDA, *, ADSBAR, BEBAR(3), BEBAR(2), BEBAR(1), BEBAR(0), BLASTBAR, DENBAR, WRBAR, DTRBAR, *, WAITBAR, BSTALL, DCBAR, SUPBAR, *, LOCKBAR, BREQ, A(31), A(30), A(29), A(28), A(27), A(26), A(25), A(24), A(23), A(22), A(21), A(20), bidir, input, input, input, output3, control, output3, output3, output3, output3, output3, output3, output3, output3, output3, control, output3, output3, output3, output3, control, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, X, X)," X)," X)," X, 1)," X, X, X, X, X, X, X, X, X, 1)," X, X, X, X, 1)," X, X, X, X, X, X, X, X, X, X, X, X, X, X, 17, 1, & & & 46, 1, & 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 61, 1, 56, 1, & 61, 1, 6, 1, Z)," Z)," Z)," Z)," & & & & Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & Z)," & Z)," & 61, 1, 61, 1, & 61, 1, 6, 1, Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & & & & & & 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 94 Advance Information Datasheet 80960HA/HD/HT Example 2. Boundary-Scan Description Language (BSDL) for PQ2 Package Example (Sheet 8 of 8) "76 (BC_1, "77 (BC_1, "78 (BC_1, "79 (BC_1, "80 (BC_1, "81 (BC_1, "82 (BC_1, "83 (BC_1, "84 (BC_1, "85 (BC_1, "86 (BC_1, "87 (BC_1, "88 (BC_1, "89 (BC_1, "90 (BC_1, "91 (BC_1, "92 (BC_1, "93 (BC_1, "94 (BC_1, "95 (BC_4, "96 (BC_4, "97 (BC_4, "98 (BC_4, "99 (BC_4, "100(BC_4, "101(BC_4, "102(BC_4, "103(BC_4, "104(BC_4, "105(BC_4, "106(BC_1, "107(BC_1, "108(BC_1, "109(BC_1, "110(BC_1, "111(BC_1, end Ha_Processor; A(19), A(18), A(17), A(16), *, A(15), A(14), A(13), A(12), A(11), A(10), A(9), A(8), A(7), A(6), A(5), A(4), A(3), A(2), NMIBAR, XINTBAR(7), XINTBAR(6), XINTBAR(5), XINTBAR(4), XINTBAR(3), XINTBAR(2), XINTBAR(1), XINTBAR(0), RESETBAR, CLKIN, CT(3), CT(2), CT(1), CT(0), PCHKBAR, *, output3, output3, output3, output3, control, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, output3, input, input, input, input, input, input, input, input, input, input, input, output3, output3, output3, output3, output3, control, X, X, X, X, 1)," X, X, X, X, X, X, X, X, X, X, X, X, X, X, X)," X)," X)," X)," X)," X)," X)," X)," X)," X)," X)," X, X, X, X, X, 1)"; 80, 1, 80, 1, 80, 1, 80, 1, & 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, 80, 1, & & & & & & & & & & & 80, 1, 80, 1, 80, 1, 80, 1, 111,1, Z)," Z)," Z)," Z)," Z)," & & & & & Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," Z)," & & & & & & & & & & & & & & Z)," Z)," Z)," Z)," & & & & Advance Information Datasheet 95 80960HA/HD/HT Table 26. Data Sheet Version -006 to -007 Revision History Section Entire data sheet "32-Bit Parallel Architecture" on page 1 Copyright Page Section 3.0, "Package Information" on page 6 Description Formatted in new template. Revised "1.2 Gbyte Internal Bandwith (75 MHz) to "1.28 Gbyte ... (80 MHz)". Updated legal text. Added paaragraph two and Table 5. Corrected minor typeset and spacing errors. Table 7 "80960Hx Processor Family Pin Descriptions" on page 8 BREQ; Revised description. ONCE; last sentence, changed "low" to "high". TDI and TMS; removed last sentence, "Pull this pin low when not in use." Figure 2 "80960Hx 168-Pin PGA Pinout -- View from Top (Pins Facing Down)" on page 12 Figure 4 "80960Hx 208-Pin PQ4 Pinout" on page 18 Table 10 "80960Hx PQ4 Pinout -- Signal Name Order" on page 19 Table 11 "80960Hx PQ4 Pinout -- Pin Number Order" on page 21 Section 4.1, "Absolute Maximum Ratings" on page 29 Section 4.5, "VCCPLL Pin Requirements" on page 31 Table 21 "80960Hx DC Characteristics" on page 32 Added insert package marking diagram. Added insert package marking diagram. Corrected TDO ("O" was zero) and revised alphabetical ordering. Corrected TDO ("O" was zero) and revised alphabetical ordering. Revised "VCC" to "VCC5" for "Voltage on Other Pins ...". Added section. Added footnote (1) to "ILO" notes column for "TDO" pin. Added footnote (10) to "CIN, COUT and CI/O" pin. Added overbars where required. Table 22 "80960Hx AC Characteristics" on page 34 Modified "TDVNH" to list separate specifications for 3.3 V and 5 V. Modified "TOV2, TOH2 and TTVEL" to reflect specific 80960HA, 80960HD and 80960HT values. Figure 23 "ICC Active (Power Supply) vs. Frequency" on page 43 Figure 49 "BREQ and BSTALL Operation" on page 66 Changed "5" to "0" on "CLKIN Frequency" axis. Added figure and following text. 96 Advance Information Datasheet |
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